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(parent: 48d13e4) | patch
hdl.mem: ensure transparent read port model has correct latency.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)
commitfa2af27bb0d0767107e7ed68f79e4fa767460d06
tree3b26f9a602fe7a8e62f1eb39c57de058745a7f7ctree
parent48d13e47ec085bb8921bf7bff77803a17cab3fe1commit | diff
hdl.mem: ensure transparent read port model has correct latency.
nmigen/hdl/mem.py diff | blob | history
nmigen/test/test_sim.py diff | blob | history