projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: a728193) | patch
Avoid mixing module port declaration styles in ice40 cells_sim.v
authorOlof Kindgren <olof.kindgren@gmail.com>
Thu, 17 May 2018 11:54:40 +0000 (13:54 +0200)
committerOlof Kindgren <olof.kindgren@gmail.com>
Thu, 17 May 2018 11:54:43 +0000 (13:54 +0200)
commitfaac2c559565a25e58ce95a7ea873df0c30375dc
treea2bf6419d36745d2d30c45f7a60060ccc57b49b9tree
parenta7281930c5877b34e072d90d5ca013f8fda7e2cccommit | diff
Avoid mixing module port declaration styles in ice40 cells_sim.v

The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
techlibs/ice40/cells_sim.v diff | blob | history