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(parent: 92e5b4b) | patch
Create atlantic.py
authorAntti Lukats <Antti.Lukats@googlemail.com>
Fri, 30 Aug 2019 07:35:10 +0000 (09:35 +0200)
committerAntti Lukats <Antti.Lukats@googlemail.com>
Fri, 30 Aug 2019 07:35:10 +0000 (09:35 +0200)
commitfb00ee85a246a53061edb4a89b3d8d26a9cd97d8
tree6643bf0e8cddefbee6e0a4e24ee1c3072be8d974tree
parent92e5b4b2cdeedd3fe5c3c140259ed79c0c7a1198commit | diff
Create atlantic.py

atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
litex/soc/cores/atlantic.py [new file with mode: 0644] blob