projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 71f1f71) | patch
back.pysim: new simulator backend (WIP).
authorwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 18:00:05 +0000 (18:00 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 18:02:46 +0000 (18:02 +0000)
commitfb27c2520b55b9bdf42d2cd81580da534a74f2db
tree4e768a9625339f9a7739dc8da7000f1e21cdb7datree
parent71f1f717c47f193d14cc7285632b7c88314f5a7bcommit | diff
back.pysim: new simulator backend (WIP).
.gitignore diff | blob | history
examples/clkdiv.py diff | blob | history
nmigen/back/pysim.py [new file with mode: 0644] blob
nmigen/fhdl/ast.py diff | blob | history
nmigen/fhdl/ir.py diff | blob | history
nmigen/test/test_fhdl_dsl.py diff | blob | history
nmigen/test/test_fhdl_value.py diff | blob | history
nmigen/test/test_fhdl_xfrm.py diff | blob | history
setup.py diff | blob | history