projects / openpower-isa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b36fa1f) | patch
bit of a reorg, adding option to test end of inner loops of SVSTATE(s)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 19 Jul 2021 19:45:25 +0000 (20:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 19 Jul 2021 19:45:25 +0000 (20:45 +0100)
commitfb899063f59a2a28358405230f3bf059c6487470
tree9dcb2d6e460659e66fd8830faec471090e265cd4tree
parentb36fa1ffff00d521df1d3f901e7f63a7bfe2f23acommit | diff
bit of a reorg, adding option to test end of inner loops of SVSTATE(s)
needed to pass the immediate to svstep as an option of which
SVSTATE0-3 to test
openpower/isa/simplev.mdwn diff | blob | history
src/openpower/decoder/isa/caller.py diff | blob | history
src/openpower/decoder/isa/remap_fft_yield.py diff | blob | history
src/openpower/decoder/isa/remapyield.py diff | blob | history
src/openpower/decoder/isa/svstate.py diff | blob | history
src/openpower/decoder/isa/test_caller_setvl.py diff | blob | history
src/openpower/decoder/isa/test_caller_svp64_fft.py diff | blob | history
src/openpower/decoder/power_pseudo.py diff | blob | history
src/openpower/decoder/pseudo/parser.py diff | blob | history