projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Wed, 18 Dec 2013 12:41:36 +0000 (13:41 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Wed, 18 Dec 2013 12:41:36 +0000 (13:41 +0100) | ||
| commit | fbd06a1afcef77e32b1fbe6405f1e639995d2fa5 | |
| tree | 941a167a848251dd026f9bbd9903a6146720c402 | tree |
| parent | 921064c20044f72a64bec12dbd73103bdd3f45e3 | commit | diff |
| frontends/verilog/preproc.cc | diff | blob | history | |
| tests/simple/macros.v | diff | blob | history |