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(parent: 95241c8) | patch
Fixed all known specify/endspecify issues, without breaking 'make test'.
authorUdi Finkelstein <github@udifink.com>
Mon, 20 Aug 2018 14:27:45 +0000 (17:27 +0300)
committerUdi Finkelstein <github@udifink.com>
Mon, 20 Aug 2018 14:27:45 +0000 (17:27 +0300)
commitfbfc677df3e54798faba3ab2f27c270759b96507
treea0a21de6d3192c219aad2d9bd2944ca25eee9e1dtree
parent95241c8f4d32c5bd644bef71509965a82582264ccommit | diff
Fixed all known specify/endspecify issues, without breaking 'make test'.
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
frontends/verilog/verilog_parser.y diff | blob | history