git.libre-soc.org Git - litex.git/commit

author	Florent Kermarrec <florent@enjoy-digital.fr>
	Fri, 13 Nov 2015 13:50:50 +0000 (14:50 +0100)
committer	Florent Kermarrec <florent@enjoy-digital.fr>
	Fri, 13 Nov 2015 17:31:46 +0000 (18:31 +0100)
commit	fc3ffe87acf6ec97784b48ac1b7a61e3b31451ea
tree	f448111cfd15b756bf03ad9b824101e12f7784c6	tree
parent	ae3d54499aac40a08bfa7b2511733d3003391b42	commit \| diff

for now use our fork of migen (to be able to simulate our designs)

69 files changed:

litex/boards/targets/de0nano.py		diff \| blob \| history
litex/boards/targets/kc705.py		diff \| blob \| history
litex/boards/targets/minispartan6.py		diff \| blob \| history
litex/boards/targets/sim.py		diff \| blob \| history
litex/boards/targets/simple.py		diff \| blob \| history
litex/build/altera/common.py		diff \| blob \| history
litex/build/altera/quartus.py		diff \| blob \| history
litex/build/generic_platform.py		diff \| blob \| history
litex/build/lattice/common.py		diff \| blob \| history
litex/build/lattice/diamond.py		diff \| blob \| history
litex/build/sim/verilator.py		diff \| blob \| history
litex/build/xilinx/common.py		diff \| blob \| history
litex/build/xilinx/ise.py		diff \| blob \| history
litex/build/xilinx/vivado.py		diff \| blob \| history
litex/gen/fhdl/verilog.py		diff \| blob \| history
litex/soc/cores/cpu/lm32/core.py		diff \| blob \| history
litex/soc/cores/cpu/mor1kx/core.py		diff \| blob \| history
litex/soc/cores/flash/nor_flash_16.py		diff \| blob \| history
litex/soc/cores/flash/spi_flash.py		diff \| blob \| history
litex/soc/cores/gpio.py		diff \| blob \| history
litex/soc/cores/identifier.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/common.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/__init__.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/__init__.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/crc.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/gap.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/last_be.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/padding.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/core/preamble.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/phy/gmii.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/phy/gmii_mii.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/phy/loopback.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/phy/mii.py		diff \| blob \| history
litex/soc/cores/liteeth_mini/phy/s6rgmii.py		diff \| blob \| history
litex/soc/cores/sdram/dfii.py		diff \| blob \| history
litex/soc/cores/sdram/lasmicon/bankmachine.py		diff \| blob \| history
litex/soc/cores/sdram/lasmicon/core.py		diff \| blob \| history
litex/soc/cores/sdram/lasmicon/multiplexer.py		diff \| blob \| history
litex/soc/cores/sdram/lasmicon/perf.py		diff \| blob \| history
litex/soc/cores/sdram/lasmicon/refresher.py		diff \| blob \| history
litex/soc/cores/sdram/minicon/core.py		diff \| blob \| history
litex/soc/cores/sdram/model.py		diff \| blob \| history
litex/soc/cores/sdram/phy/gensdrphy.py		diff \| blob \| history
litex/soc/cores/sdram/phy/k7ddrphy.py		diff \| blob \| history
litex/soc/cores/sdram/phy/s6ddrphy.py		diff \| blob \| history
litex/soc/cores/sdram/settings.py		diff \| blob \| history
litex/soc/cores/sdram/tester.py		diff \| blob \| history
litex/soc/cores/spi/core.py		diff \| blob \| history
litex/soc/cores/spi/test.py		diff \| blob \| history
litex/soc/cores/timer.py		diff \| blob \| history
litex/soc/cores/uart/bridge.py		diff \| blob \| history
litex/soc/cores/uart/core.py		diff \| blob \| history
litex/soc/integration/cpu_interface.py		diff \| blob \| history
litex/soc/integration/sdram_init.py		diff \| blob \| history
litex/soc/integration/soc_core.py		diff \| blob \| history
litex/soc/integration/soc_sdram.py		diff \| blob \| history
litex/soc/interconnect/csr.py		diff \| blob \| history
litex/soc/interconnect/csr_bus.py		diff \| blob \| history
litex/soc/interconnect/csr_eventmanager.py		diff \| blob \| history
litex/soc/interconnect/dfi.py		diff \| blob \| history
litex/soc/interconnect/dma_lasmi.py		diff \| blob \| history
litex/soc/interconnect/lasmi_bus.py		diff \| blob \| history
litex/soc/interconnect/packet.py		diff \| blob \| history
litex/soc/interconnect/stream.py		diff \| blob \| history
litex/soc/interconnect/wishbone.py		diff \| blob \| history
litex/soc/interconnect/wishbone2csr.py		diff \| blob \| history
litex/soc/interconnect/wishbone2lasmi.py		diff \| blob \| history
litex/soc/interconnect/wishbonebridge.py		diff \| blob \| history

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