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sim: bfin: add missing VS set with add/sub insns
authorMike Frysinger <vapier@gentoo.org>
Sat, 26 Mar 2011 06:02:41 +0000 (06:02 +0000)
committerMike Frysinger <vapier@gentoo.org>
Sat, 26 Mar 2011 06:02:41 +0000 (06:02 +0000)
commitfcd1ee07d35e970766622ea09e79a9b80c632cf9
tree3de69cc7320cca78c6161d015fb7e7e6f3460958tree
parent81723326fe1126b9dfd48e99b65ba52e333ede58commit | diff
sim: bfin: add missing VS set with add/sub insns

The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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sim/bfin/bfin-sim.c diff | blob | history