git.libre-soc.org Git - gem5.git/commit

author	Andreas Sandberg <andreas.sandberg@arm.com>
	Thu, 7 Apr 2016 09:42:07 +0000 (10:42 +0100)
committer	Andreas Sandberg <andreas.sandberg@arm.com>
	Thu, 7 Apr 2016 09:42:07 +0000 (10:42 +0100)
commit	fd52a63e24fe047e1dafc48e5da9b4ce1b086c49
tree	65a7eef6c12995b1215ce5b0622da7732fd87cea	tree
parent	be28d96510e0e722db83b26f1a12d3f5de979b32	commit \| diff

Revert to 74c1e6513bd0 (sim: Thermal support for Linux)

24 files changed:

src/arch/alpha/tlb.cc		diff \| blob \| history
src/arch/mips/tlb.cc		diff \| blob \| history
src/arch/power/tlb.cc		diff \| blob \| history
src/cpu/testers/memtest/memtest.cc		diff \| blob \| history
src/dev/arm/flash_device.cc		diff \| blob \| history
src/dev/arm/hdlcd.cc		diff \| blob \| history
src/dev/arm/ufs_device.cc		diff \| blob \| history
src/mem/probes/stack_dist.cc		diff \| blob \| history
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc		diff \| blob \| history
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc		diff \| blob \| history
src/mem/ruby/network/simple/SimpleNetwork.cc		diff \| blob \| history
src/mem/ruby/network/simple/Switch.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.cc		diff \| blob \| history
src/mem/ruby/structures/CacheMemory.cc		diff \| blob \| history
src/mem/ruby/structures/Prefetcher.cc		diff \| blob \| history
src/mem/ruby/system/RubySystem.hh		diff \| blob \| history
src/mem/ruby/system/Sequencer.cc		diff \| blob \| history
src/mem/snoop_filter.cc		diff \| blob \| history
src/sim/ClockedObject.py		diff \| blob \| history
src/sim/SConscript		diff \| blob \| history
src/sim/clock_domain.cc		diff \| blob \| history
src/sim/clocked_object.cc	[deleted file]	blob \| history
src/sim/clocked_object.hh		diff \| blob \| history
src/sim/voltage_domain.cc		diff \| blob \| history