projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Fri, 16 Jan 2015 13:59:40 +0000 (14:59 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Fri, 16 Jan 2015 13:59:40 +0000 (14:59 +0100) | ||
| commit | fd8c8d4fd386c225b13ec02f47ce32905b9eb7d2 | |
| tree | 7c800aab0882c35dc4035fe3e3915518b3f005cc | tree |
| parent | b197279f3c2d7b487d69cafca8dfc5edb4b2eaa8 | commit | diff |
| techlibs/xilinx/cells_sim.v | diff | blob | history |