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(parent: d4022fa) | patch
ClockDomain.{rst→reset}, for consistency with ResetInserter.
authorwhitequark <cz@m-labs.hk>
Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)
committerwhitequark <cz@m-labs.hk>
Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)
commitfd9408e1317c07aa0f9898024ea3a94f1390a748
treec5fe13dd20cc10aaecf72a543bda4959c39b6bb1tree
parentd4022fa273d29fa20c5a839b4258cdbb7dcbafffcommit | diff
ClockDomain.{rst→reset}, for consistency with ResetInserter.

nmigen.compat.ClockDomain would alias this, for Migen compatibility.
examples/arst.py diff | blob | history
nmigen/back/rtlil.py diff | blob | history
nmigen/fhdl/cd.py diff | blob | history
nmigen/fhdl/ir.py diff | blob | history