projects / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: e457454) | patch
radeonsi/gfx9: add support for PIPE_ALIGNED=0
authorMarek Olšák <marek.olsak@amd.com>
Fri, 9 Nov 2018 21:51:47 +0000 (16:51 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 4 Apr 2019 13:53:24 +0000 (09:53 -0400)
commitfe3bfd7971bf20a663e949a0a5633492a9412889
tree5572229f138fdc3be5bc987eebf773260fd582a1tree
parente457454cb6279ffaeb4c913fa812249e7e81e1e8commit | diff
radeonsi/gfx9: add support for PIPE_ALIGNED=0

Needed by displayable DCC.

We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
src/gallium/drivers/radeonsi/si_blit.c diff | blob | history
src/gallium/drivers/radeonsi/si_compute_blit.c diff | blob | history
src/gallium/drivers/radeonsi/si_pipe.h diff | blob | history
src/gallium/drivers/radeonsi/si_state.c diff | blob | history