merge most of misoc 54e1ef82 and migen e93d0601 changes
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 13 Jan 2017 00:33:48 +0000 (01:33 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 13 Jan 2017 02:55:00 +0000 (03:55 +0100)
commitff31959aea1e3815d95798996c3999f122314ae6
tree308255a4d28dcd0c8ea95322e761dadadadbb748
parent2507eff890e8d4ebbdb0e88c9b0f85923054b175
merge most of misoc 54e1ef82 and migen e93d0601 changes
41 files changed:
litex/boards/targets/kc705.py
litex/boards/targets/nexys_video.py
litex/build/altera/quartus.py
litex/build/tools.py
litex/build/xilinx/common.py
litex/build/xilinx/ise.py
litex/build/xilinx/platform.py
litex/build/xilinx/vivado.py
litex/gen/__init__.py
litex/gen/fhdl/bitcontainer.py
litex/gen/fhdl/decorators.py
litex/gen/fhdl/simplify.py
litex/gen/fhdl/specials.py
litex/gen/fhdl/structure.py
litex/gen/fhdl/verilog.py
litex/gen/fhdl/visit.py
litex/gen/genlib/cdc.py
litex/gen/genlib/fifo.py
litex/gen/genlib/fsm.py
litex/gen/genlib/io.py
litex/gen/sim/core.py
litex/soc/integration/builder.py
litex/soc/integration/cpu_interface.py
litex/soc/integration/soc_core.py
litex/soc/integration/soc_sdram.py
litex/soc/interconnect/csr.py
litex/soc/interconnect/csr_bus.py
litex/soc/interconnect/csr_eventmanager.py
litex/soc/interconnect/wishbone.py
litex/soc/software/bios/boot.c
litex/soc/software/bios/boot.h
litex/soc/software/bios/main.c
litex/soc/software/include/base/inttypes.h
litex/soc/software/include/base/math.h [new file with mode: 0644]
litex/soc/software/include/base/stddef.h
litex/soc/software/include/base/stdlib.h
litex/soc/software/include/dyld/dyld.h
litex/soc/software/include/fdlibm/fdlibm.h [new file with mode: 0644]
litex/soc/software/libbase/crt0-or1k.S
litex/soc/software/libbase/exception.c
litex/soc/software/libbase/vsnprintf.c