Split module ports, 20 per line
authorMiodrag Milanovic <mmicko@gmail.com>
Sat, 9 Oct 2021 11:40:55 +0000 (13:40 +0200)
committerMiodrag Milanovic <mmicko@gmail.com>
Sat, 9 Oct 2021 11:40:55 +0000 (13:40 +0200)
commitff8e999a7112a1975d268e6ebb3e751f6f0364c7
treef2ea2e1e5992146032348b2572dd4afae9a9d935
parentd8f6d7b18d23a588fc537f12aef3c4c8ddbe3418
Split module ports, 20 per line
backends/verilog/verilog_backend.cc