litesata/example_designs: Add missing clock in phy instantiation
authorOlof Kindgren <olof.kindgren@gmail.com>
Thu, 25 Jun 2015 23:15:34 +0000 (01:15 +0200)
committerOlof Kindgren <olof.kindgren@gmail.com>
Thu, 25 Jun 2015 23:20:25 +0000 (01:20 +0200)
commitffb6081720eb1d4254dd774680d5b203e65cd271
treec1cd11f02becae78bb5a58f96b896476ab640d61
parent125432b5b69e46ed456f0cdc8fbd4b61a3b0c735
litesata/example_designs: Add missing clock in phy instantiation
misoclib/mem/litesata/example_designs/targets/core.py