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(parent: 5581fdc) | patch
back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.
authorwhitequark <whitequark@whitequark.org>
Sun, 25 Oct 2020 01:59:46 +0000 (01:59 +0000)
committerwhitequark <whitequark@whitequark.org>
Sun, 25 Oct 2020 01:59:46 +0000 (01:59 +0000)
commit87454b0b6f28fe1856e6de676cc4bffe95135744
tree45bec823a787887f8e816125abd040c35dc65889tree
parent5581fdc1e84d691ab6f7998b80500a18cfd43c9fcommit | diff
back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.

To track upstream changes.
nmigen/back/rtlil.py diff | blob | history
nmigen/back/verilog.py diff | blob | history