projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: abbebf8) | patch
vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.
authorwhitequark <whitequark@whitequark.org>
Fri, 6 Nov 2020 01:31:14 +0000 (01:31 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 6 Nov 2020 01:31:14 +0000 (01:31 +0000)
commitc6150d05867bea1a7266e3c950d3d9846ba7ed58
tree6e87c417ba4c37d62088a08927ab7c5885800ebftree
parentabbebf8efe931938f0de95d041f1d91c693efddccommit | diff
vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.

These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
nmigen/vendor/lattice_ecp5.py diff | blob | history
nmigen/vendor/lattice_ice40.py diff | blob | history