projects
/
sifive-blocks.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
00086c2
)
Add missing cloneType methods to pin bundles
author
Megan Wachs
<megan@sifive.com>
Thu, 20 Jul 2017 18:36:31 +0000
(11:36 -0700)
committer
Megan Wachs
<megan@sifive.com>
Thu, 20 Jul 2017 18:36:31 +0000
(11:36 -0700)
src/main/scala/devices/i2c/I2CPins.scala
patch
|
blob
|
history
src/main/scala/devices/pwm/PWMPeriphery.scala
patch
|
blob
|
history
src/main/scala/devices/spi/SPIPins.scala
patch
|
blob
|
history
src/main/scala/devices/uart/UARTPeriphery.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/devices/i2c/I2CPins.scala
b/src/main/scala/devices/i2c/I2CPins.scala
index df6dd6f3bd13d33da2e4025e5135f39008f0d877..8e17765b908a48511db73f27acd0b1d953b5dbad 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPins.scala
+++ b/
src/main/scala/devices/i2c/I2CPins.scala
@@
-12,6
+12,9
@@
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
val scl: T = pingen()
val sda: T = pingen()
val scl: T = pingen()
val sda: T = pingen()
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+
def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
diff --git
a/src/main/scala/devices/pwm/PWMPeriphery.scala
b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 31ad5f6f3a999dc32de46efc8b6149ce4beb7429..f83cbafdfe9780ea83e865a8d94b65c4de9a8c4a 100644
(file)
--- a/
src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/
src/main/scala/devices/pwm/PWMPeriphery.scala
@@
-18,6
+18,9
@@
class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
val pwm: Vec[T] = Vec(c.ncmp, pingen())
val pwm: Vec[T] = Vec(c.ncmp, pingen())
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
def fromPWMPort(port: PWMPortIO) {
(pwm zip port.port) foreach {case (pin, port) =>
pin.outputPin(port)
def fromPWMPort(port: PWMPortIO) {
(pwm zip port.port) foreach {case (pin, port) =>
pin.outputPin(port)
diff --git
a/src/main/scala/devices/spi/SPIPins.scala
b/src/main/scala/devices/spi/SPIPins.scala
index 346f8ee63d820e6fae8436858332b06ebe0b04a8..4307fadbd71a455cd43500eb2ff81dbed429cd68 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPins.scala
+++ b/
src/main/scala/devices/spi/SPIPins.scala
@@
-7,9
+7,12
@@
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
- val sck: T = pingen()
- val dq: Vec[T] = Vec(4, pingen())
- val cs: Vec[T] = Vec(c.csWidth, pingen())
+ val sck = pingen()
+ val dq = Vec(4, pingen())
+ val cs = Vec(c.csWidth, pingen())
+
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index d94d5180941502ff3e3bc0f872d248f582c973d0..105592d2042e7a6f19d265d37c45f3e5ff771c46 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-44,6
+44,9
@@
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
val rxd = pingen()
val txd = pingen()
val rxd = pingen()
val txd = pingen()
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+
def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)