- def add_ram(self, name, origin, size, contents=[], mode="rw", bus=None):
- if bus is None:
- bus = wishbone.Interface(data_width=self.bus.data_width)
-
- if isinstance(bus, wishbone.Interface):
- ram = wishbone.SRAM(size, bus=bus, init=contents, read_only=(mode == "r"))
- elif isinstance(bus, axi.AXILiteInterface):
- ram = axi.AXILiteSRAM(size, bus=bus, init=contents, read_only=(mode == "r"))
- else:
- raise TypeError(bus)
-
+ def add_ram(self, name, origin, size, contents=[], mode="rw"):
+ ram_bus = wishbone.Interface(data_width=self.bus.data_width)
+ ram = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=(mode == "r"))