This bit redirects the state cache from the unified/RO sections of the
L3 cache to the "CS command buffer" section of the cache, which would
be set up via TCCNTLREG. The documentation says:
"Additionaly, this redirection should be enabled only if there is a
non-zero allocation for the CS command buffer section."
We don't allocate any cache to the CS command buffer section, so
enabling this redirection effectively disabled the state cache.
The Windows driver only sets up that section when using POSH, which
we do not currently use. So, leave it unallocated and disable the
redirection to get a functional state cache again.
Improves performance in Civilization VI by 18%, Manhattan 3.0 by 6%,
and Car Chase by 2%.
}
iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
}
iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
- iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1), ®_val, reg) {
- reg.StateCacheRedirectToCSSectionEnable = true;
- reg.StateCacheRedirectToCSSectionEnableMask = true;
- }
- iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
-
/* Hardware specification recommends disabling repacking for the
* compatibility with decompression mechanism in display controller.
*/
/* Hardware specification recommends disabling repacking for the
* compatibility with decompression mechanism in display controller.
*/
lri.DataDWord = half_slice_chicken7;
}
lri.DataDWord = half_slice_chicken7;
}
- /* WaEnableStateCacheRedirectToCS:icl */
- uint32_t slice_common_eco_chicken1;
- anv_pack_struct(&slice_common_eco_chicken1,
- GENX(SLICE_COMMON_ECO_CHICKEN1),
- .StateCacheRedirectToCSSectionEnable = true,
- .StateCacheRedirectToCSSectionEnableMask = true);
-
- anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(SLICE_COMMON_ECO_CHICKEN1_num);
- lri.DataDWord = slice_common_eco_chicken1;
- }
-
#endif
genX(emit_slice_hashing_state)(device, &batch);
#endif
genX(emit_slice_hashing_state)(device, &batch);
*/
brw_load_register_imm32(brw, GEN8_L3CNTLREG,
GEN8_L3CNTLREG_EDBC_NO_HANG);
*/
brw_load_register_imm32(brw, GEN8_L3CNTLREG,
GEN8_L3CNTLREG_EDBC_NO_HANG);
-
- /* WaEnableStateCacheRedirectToCS:icl */
- brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1,
- GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE |
- REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE));
}
/* hardware specification recommends disabling repacking for
}
/* hardware specification recommends disabling repacking for