projects
/
riscv-tests.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
2f4a658
)
Fix illegal-instruction test when S-mode is not implemented
author
Andrew Waterman
<andrew@sifive.com>
Sat, 15 Apr 2017 01:11:49 +0000
(18:11 -0700)
committer
Andrew Waterman
<andrew@sifive.com>
Sat, 15 Apr 2017 01:11:49 +0000
(18:11 -0700)
isa/rv64mi/illegal.S
patch
|
blob
|
history
diff --git
a/isa/rv64mi/illegal.S
b/isa/rv64mi/illegal.S
index 30105e68d61df08741e14d560e35fb736bb150e3..a1b445f0df08c7b3b47ab9b9fe41d62f4e115d08 100644
(file)
--- a/
isa/rv64mi/illegal.S
+++ b/
isa/rv64mi/illegal.S
@@
-21,6
+21,15
@@
bad2:
.word 0
j fail
.word 0
j fail
+ # Skip the rest of the test if S-mode is not present.
+ li t0, MSTATUS_MPP
+ csrc mstatus, t0
+ li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+ csrs mstatus, t1
+ csrr t2, mstatus
+ and t2, t2, t0
+ bne t1, t2, pass
+
# Test vectored interrupts if they are supported.
test_vectored_interrupts:
csrwi mip, MIP_SSIP
# Test vectored interrupts if they are supported.
test_vectored_interrupts:
csrwi mip, MIP_SSIP
@@
-33,23
+42,18
@@
test_vectored_interrupts:
csrsi mstatus, MSTATUS_MIE
1:
j 1b
csrsi mstatus, MSTATUS_MIE
1:
j 1b
-
msip:
csrw mtvec, s0
msip:
csrw mtvec, s0
- # Skip the rest of the test if S-mode is not present.
- li t0, MSTATUS_MPP
- csrc mstatus, t0
- li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
- csrs mstatus, t1
- csrr t2, mstatus
- and t2, t2, t0
- bne t1, t2, pass
-
# Delegate supervisor software interrupts so WFI won't stall.
csrwi mideleg, MIP_SSIP
# Delegate supervisor software interrupts so WFI won't stall.
csrwi mideleg, MIP_SSIP
+ # Enter supervisor mode.
la t0, 1f
csrw mepc, t0
la t0, 1f
csrw mepc, t0
+ li t0, MSTATUS_MPP
+ csrc mstatus, t0
+ li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+ csrs mstatus, t1
mret
1:
mret
1: