Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap");
Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap");
- Pass::call(holes_module->design, "clean -purge");
+ for (auto cell : holes_module->cells())
+ if (!cell->type.in("$_NOT_", "$_AND_"))
+ log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);