+ if (req->isUncacheable()) {
+ // Funky Turbolaser mailbox access...don't update
+ // result register (see stq_c in decoder.isa)
+ req->setExtraData(2);
+ } else {
+ // standard store conditional
+ if (!lock_flag || (req->getPaddr()&~0xF) != lock_addr) {
+ // Lock flag not set or addr mismatch in CPU;
+ // don't even bother sending to memory system
+ req->setExtraData(0);
+ lock_flag = false;
+
+ // the rest of this code is not architectural;
+ // it's just a debugging aid to help detect
+ // livelock by warning on long sequences of failed
+ // store conditionals
+ int stCondFailures = xc->readStCondFailures();
+ stCondFailures++;
+ xc->setStCondFailures(stCondFailures);
+ if (stCondFailures % 100000 == 0) {
+ warn("%i:"" context %d:"
+ " %d consecutive store conditional failures\n",
+ curTick(), xc->contextId(), stCondFailures);
+ }
+
+ if (!lock_flag){
+ DPRINTF(LLSC, "[cid:%i]:"
+ " Lock Flag Set, Store Conditional Failed.\n",
+ req->contextId());
+ } else if ((req->getPaddr() & ~0xf) != lock_addr) {
+ DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
+ "Store Conditional Failed.\n", req->contextId());
+ }
+ // store conditional failed already, so don't issue it to mem
+ return false;
+ }
+ }
+