for shift-by-register opcodes.
Bug found by testsuite.
Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com)
Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com)
+ * mn10300-opc.c (mn10300_opcodes): Fix destination register
+ for shift-by-register opcodes.
+
* mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
into [AD][MN][01] for encoding the position of the register
in the opcode.
* mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
into [AD][MN][01] for encoding the position of the register
in the opcode.
{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
-{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN1}},
+{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
-{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN1}},
+{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
-{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN1}},
+{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},