Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
}
if (sctx->do_update_shaders && !si_update_shaders(sctx))
}
if (sctx->do_update_shaders && !si_update_shaders(sctx))
if (index_size) {
/* Translate or upload, if needed. */
if (index_size) {
/* Translate or upload, if needed. */
* need_cs_space flush before we add buffers to the buffer list.
*/
if (!si_upload_vertex_buffer_descriptors(sctx))
* need_cs_space flush before we add buffers to the buffer list.
*/
if (!si_upload_vertex_buffer_descriptors(sctx))
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
if (!si_upload_graphics_shader_descriptors(sctx))
masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
if (!si_upload_graphics_shader_descriptors(sctx))
/* Emit all states except possibly render condition. */
si_emit_all_states(sctx, info, masked_atoms);
/* Emit all states except possibly render condition. */
si_emit_all_states(sctx, info, masked_atoms);
if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
sctx->num_spill_draw_calls++;
}
if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
sctx->num_spill_draw_calls++;
}
if (index_size && indexbuf != info->index.resource)
pipe_resource_reference(&indexbuf, NULL);
}
if (index_size && indexbuf != info->index.resource)
pipe_resource_reference(&indexbuf, NULL);
}