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Capitalisation
authorEddie Hung <eddie@fpgeh.com>
Thu, 27 Jun 2019 18:26:44 +0000 (11:26 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 27 Jun 2019 18:50:12 +0000 (11:50 -0700)
CHANGELOG patch | blob | history

diff --git a/CHANGELOG b/CHANGELOG
index 6931c3de007c943ca56f31ca69896648e2af76fc..6f476a2cb82c2a1fa3dc8966fcb933ff750a837f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -47,7 +47,7 @@ Yosys 0.7 .. Yosys 0.8
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
-    - Added support for systemVerilog "++" and "--" operators
+    - Added support for SystemVerilog "++" and "--" operators
     - Added support for SystemVerilog unique, unique0, and priority case
     - Added "write_edif" options for edif "flavors"
     - Added support for resetall compiler directive
     - Added support for SystemVerilog unique, unique0, and priority case
     - Added "write_edif" options for edif "flavors"
     - Added support for resetall compiler directive