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Cleanup
author
Eddie Hung
<eddie@fpgeh.com>
Fri, 12 Jul 2019 22:31:02 +0000
(15:31 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Sat, 13 Jul 2019 02:30:18 +0000
(19:30 -0700)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 224a2d504509fb27301a6b3ef8d33abbd3aa78af..f6592098b71475838daa39438ebc656e4f464af4 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-756,7
+756,6
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
log_assert(driving_lut);
RTLIL::SigBit a_bit = not_cell->getPort("\\A");
RTLIL::SigBit y_bit = not_cell->getPort("\\Y");
log_assert(driving_lut);
RTLIL::SigBit a_bit = not_cell->getPort("\\A");
RTLIL::SigBit y_bit = not_cell->getPort("\\Y");
- driving_lut = module->cell(remap_name(driving_lut->name));
log_assert(driving_lut);
RTLIL::Const driver_lut = driving_lut->getParam("\\LUT");
for (auto &b : driver_lut.bits) {
log_assert(driving_lut);
RTLIL::Const driver_lut = driving_lut->getParam("\\LUT");
for (auto &b : driver_lut.bits) {
@@
-772,11
+771,6
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (sink_cell->type != "$lut")
goto duplicate_lut;
if (sink_cell->type != "$lut")
goto duplicate_lut;
- //static int count = 0;
- //log_warning("%d\n", count);
- //if (count++ >= 41)
- // goto duplicate_lut;
-
for (auto sink_cell : it->second) {
SigSpec A = sink_cell->getPort("\\A");
RTLIL::Const mask = sink_cell->getParam("\\LUT");
for (auto sink_cell : it->second) {
SigSpec A = sink_cell->getPort("\\A");
RTLIL::Const mask = sink_cell->getParam("\\LUT");
@@
-805,7
+799,7
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
duplicate_lut:
auto not_cell_name = not_cell->name;
module->remove(not_cell);
duplicate_lut:
auto not_cell_name = not_cell->name;
module->remove(not_cell);
-#if
0
+#if
1
auto driver_a = driving_lut->getPort("\\A").chunks();
for (auto &chunk : driver_a)
chunk.wire = module->wires_[remap_name(chunk.wire->name)];
auto driver_a = driving_lut->getPort("\\A").chunks();
for (auto &chunk : driver_a)
chunk.wire = module->wires_[remap_name(chunk.wire->name)];