+#define NVE4_COMPUTE_MEM_BARRIER_UNK0__MASK 0x00000007
+#define NVE4_COMPUTE_MEM_BARRIER_UNK0__SHIFT 0
+#define NVE4_COMPUTE_MEM_BARRIER_UNK4 0x00000010
+#define NVE4_COMPUTE_MEM_BARRIER_UNK12 0x00001000
+
+#define NVE4_COMPUTE_UNK0240 0x00000240
+
+#define NVE4_COMPUTE_UNK244_TIC_FLUSH 0x00000244
+
+#define NVE4_COMPUTE_UNK0248 0x00000248
+#define NVE4_COMPUTE_UNK0248_UNK0__MASK 0x0000003f
+#define NVE4_COMPUTE_UNK0248_UNK0__SHIFT 0
+#define NVE4_COMPUTE_UNK0248_UNK8__MASK 0x00ffff00
+#define NVE4_COMPUTE_UNK0248_UNK8__SHIFT 8
+
+#define NVE4_COMPUTE_UNK0274 0x00000274
+
+#define NVE4_COMPUTE_UNK0278 0x00000278
+
+#define NVE4_COMPUTE_UNK027C 0x0000027c