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Do not call "setundef -zero" in abc9
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 20 Jun 2019 17:22:14 +0000
(10:22 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Fri, 21 Jun 2019 00:38:04 +0000
(17:38 -0700)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 2f670dba236caaabd2eabb7ef9fa1fd08b242099..fc9da11732341260d5bac1a9e740a82ff5700345 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-380,9
+380,6
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
- Pass::call(design, "setundef -zero");
-
Pass::call(design, "aigmap");
handle_loops(design);
Pass::call(design, "aigmap");
handle_loops(design);
@@
-406,7
+403,7
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
reader.parse_xaiger();
}
ifs.close();
reader.parse_xaiger();
}
ifs.close();
- Pass::call(design, stringf("write_verilog -noexpr -norename
%s/%s", tempdir_name.c_str(), "input.v
"));
+ Pass::call(design, stringf("write_verilog -noexpr -norename"));
design->remove(design->module("$__abc9__"));
#endif
design->remove(design->module("$__abc9__"));
#endif
@@
-479,7
+476,7
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
ifs.close();
#if 0
ifs.close();
#if 0
- Pass::call(design, stringf("write_verilog -noexpr -norename
%s/%s", tempdir_name.c_str(), "output.v
"));
+ Pass::call(design, stringf("write_verilog -noexpr -norename"));
#endif
log_header(design, "Re-integrating ABC9 results.\n");
#endif
log_header(design, "Re-integrating ABC9 results.\n");