data, so that "bc" is available to 68040 cache instructions. Added
"tt0", "tt1", and
68ec030 variants.
(md_assemble): Complain if 68000 (only) and 68881 are specified.
(enum _register): Added TT0, TT1.
(m68k_ip, cases '3' and 't'): Handle new operand type codes. Pass
line number correctly in "internal error" messages. Don't print
architecture-mismatch message for operand errors.
From Colin Smith (colin@wrs.com):
* config/tc-m68k.c (m68k_ip, case '_'): Use addword twice rather than
install_operand.
+ DRP, /* 68851 or 68030 MMU regs */
+ PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
+ and ACUSR on 68ec030 */
PCSR,
IC, /* instruction cache token */
PCSR,
IC, /* instruction cache token */
NC, /* no cache token */
BC, /* both caches token */
NC, /* no cache token */
BC, /* both caches token */
+ TT0, /* 68030 access control unit regs */
+ TT1,
};
/* Internal form of an operand. */
};
/* Internal form of an operand. */
+ case '3':
+ if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
+ losing++;
+ break;
+
case 'A':
if(opP->mode!=AREG)
losing++;
case 'A':
if(opP->mode!=AREG)
losing++;
+ case 't':
+ if (opP->mode != IMMED)
+ losing++;
+ else
+ {
+ long t = get_num (opP->con1, 80);
+ if (t < 0 || t > 7 || isvar (opP->con1))
+ losing++;
+ }
+ break;
+
case 'U':
if(opP->mode!=MSCR || opP->reg!=USP)
losing++;
case 'U':
if(opP->mode!=MSCR || opP->reg!=USP)
losing++;
/* JF these are out of order. We could put them
in order if we were willing to put up with
/* JF these are out of order. We could put them
in order if we were willing to put up with
- bunches of #ifdef m68851s in the code */
+ bunches of #ifdef m68851s in the code.
+
+ Don't forget that you need these operands
+ to use 68030 MMU instructions. */
#ifndef NO_68851
/* Memory addressing mode used by pflushr */
case '|':
#ifndef NO_68851
/* Memory addressing mode used by pflushr */
case '|':
- if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
- opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
+ if (opP->mode != MSCR
+ || (opP->reg != TC && opP->reg != CAL
+ && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
- if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
- opP->reg != CRP))
+ if (opP->mode != MSCR
+ || (opP->reg != DRP && opP->reg != SRP
+ && opP->reg != CRP))
- as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
+ as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
*s, __LINE__, __FILE__);
} /* switch on type of operand */
*s, __LINE__, __FILE__);
} /* switch on type of operand */
opcode = opcode->m_next;
if (!opcode) {
opcode = opcode->m_next;
if (!opcode) {
+ if (ok_arch
+ && !(ok_arch & current_architecture))
{
char buf[200], *cp;
int len;
{
char buf[200], *cp;
int len;
switch (ok_arch)
{
case mfloat:
switch (ok_arch)
{
case mfloat:
+ strcpy (cp, "fpu (68040 or 68881/68882)");
+ strcpy (cp, "mmu (68030 or 68851)");
break;
case m68020up:
strcpy (cp, "68020 or higher");
break;
case m68020up:
strcpy (cp, "68020 or higher");
know(opP->reg == PCSR);
break;
#endif /* m68851 */
know(opP->reg == PCSR);
break;
#endif /* m68851 */
+ case '3':
+ switch (opP->reg)
+ {
+ case TT0:
+ tmpreg = 2;
+ break;
+ case TT1:
+ tmpreg = 3;
+ break;
+ default:
+ as_fatal ("failed sanity check");
+ }
+ install_operand (s[1], tmpreg);
+ break;
+ case 't':
+ tmpreg = get_num (opP->con1, 20);
+ install_operand (s[1], tmpreg);
+ break;
+ case '_': /* used only for move16 absolute 32-bit address */
tmpreg=get_num(opP->con1,80);
tmpreg=get_num(opP->con1,80);
- install_operand(s[1], tmpreg);
+ addword (tmpreg >> 16);
+ addword (tmpreg & 0xFFFF);
- as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__);
+ as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
+ s[0], __LINE__, __FILE__);
}
}
/* By the time whe get here (FINALLY) the_ins contains the complete
}
}
/* By the time whe get here (FINALLY) the_ins contains the complete
symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
}
symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
}
"d0", DATA0,
"d1", DATA1,
"d2", DATA2,
"d0", DATA0,
"d1", DATA1,
"d2", DATA2,
"ac", AC,
"bc", BC,
"cal", CAL,
"ac", AC,
"bc", BC,
"cal", CAL,
"bac5", BAC5,
"bac6", BAC6,
"bac7", BAC7,
"bac5", BAC5,
"bac6", BAC6,
"bac7", BAC7,
"ic", IC,
"dc", DC,
"nc", NC,
"ic", IC,
"dc", DC,
"nc", NC,
+ "tt0", TT0,
+ "tt1", TT1,
+ /* 68ec030 versions of same */
+ "ac0", TT0,
+ "ac1", TT1,
+ /* 68ec030 access control unit, identical to 030 MMU status reg */
+ "acusr", PSR,
+
{
int i;
for (i = 0; init_table[i].name; i++)
{
int i;
for (i = 0; init_table[i].name; i++)
insert_reg(init_table[i].name, init_table[i].number);
insert_reg(init_table[i].name, init_table[i].number);
int m,n = 0;
char *to_beg_P;
int shorts_this_frag;
int m,n = 0;
char *to_beg_P;
int shorts_this_frag;
+ static int done_first_time;
-
- if (cpu_of_arch (current_architecture) == 0)
- enum m68k_architecture cpu_type;
+ done_first_time = 1;
+
+ if (cpu_of_arch (current_architecture) == 0)
+ {
+ enum m68k_architecture cpu_type;
- if (strcmp (TARGET_CPU, "m68000") == 0)
- cpu_type = m68000;
- else if (strcmp (TARGET_CPU, "m68010") == 0)
- cpu_type = m68010;
- else if (strcmp (TARGET_CPU, "m68020") == 0
- || strcmp (TARGET_CPU, "m68k") == 0)
- cpu_type = m68020;
- else if (strcmp (TARGET_CPU, "m68030") == 0)
- cpu_type = m68030;
- else if (strcmp (TARGET_CPU, "m68040") == 0)
- cpu_type = m68040;
- else
- cpu_type = m68020;
+ if (strcmp (TARGET_CPU, "m68000") == 0)
+ cpu_type = m68000;
+ else if (strcmp (TARGET_CPU, "m68010") == 0)
+ cpu_type = m68010;
+ else if (strcmp (TARGET_CPU, "m68020") == 0
+ || strcmp (TARGET_CPU, "m68k") == 0)
+ cpu_type = m68020;
+ else if (strcmp (TARGET_CPU, "m68030") == 0)
+ cpu_type = m68030;
+ else if (strcmp (TARGET_CPU, "m68040") == 0)
+ cpu_type = m68040;
+ else
+ cpu_type = m68020;
- /* If float or mmu were specified, just default cpu. */
- if (current_architecture != 0)
- current_architecture |= cpu_type;
- else
- {
- if ((cpu_type & m68020up) != 0)
- current_architecture = (cpu_type
+ /* If float or mmu were specified, just default cpu. */
+ if (current_architecture != 0)
+ current_architecture |= cpu_type;
+ else
+ {
+ if ((cpu_type & m68020up) != 0)
+ current_architecture = (cpu_type
- );
- else
- current_architecture = cpu_type;
+ );
+ else
+ current_architecture = cpu_type;
+ }
+ }
+ if (cpu_of_arch (current_architecture) == m68000
+ && (current_architecture & m68881) != 0)
+ {
+ as_bad ("incompatible processors 68000 and 68881 specified");
}
memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
}
memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */