+void specialize(RTLIL::Module *module, const QbfSolutionType &ret) {
+ std::map<std::string, std::string> hole_loc_to_name;
+ for (auto cell : module->cells()) {
+ std::string cell_src = cell->get_src_attribute();
+ auto pos = ret.hole_to_value.find(cell_src);
+ if (pos != ret.hole_to_value.end()) {
+ log_assert(cell->type.in("$anyconst", "$anyseq"));
+ log_assert(cell->hasPort(ID::Y));
+ log_assert(cell->getPort(ID::Y).is_wire());
+ hole_loc_to_name[pos->first] = cell->getPort(ID::Y).as_wire()->name.str();
+ }
+ }
+ for (auto &it : ret.hole_to_value) {
+ std::string hole_loc = it.first;
+ std::string hole_value = it.second;
+
+ auto pos = hole_loc_to_name.find(hole_loc);
+ log_assert(pos != hole_loc_to_name.end());
+
+ std::string hole_name = hole_loc_to_name[hole_loc];
+ RTLIL::Wire *wire = module->wire(hole_name);
+ log_assert(wire != nullptr);
+
+ log("Specializing %s with %s = %d'b%s.\n", module->name.c_str(), hole_name.c_str(), wire->width, hole_value.c_str());
+ std::vector<RTLIL::SigBit> value_bv;
+ value_bv.reserve(wire->width);
+ for (char c : hole_value)
+ value_bv.push_back(c == '1'? RTLIL::S1 : RTLIL::S0);
+ std::reverse(value_bv.begin(), value_bv.end());
+ module->connect(wire, value_bv);
+ }
+}
+