- altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
- .clock_enable_input_a ("ALTERNATE" ),
- .clock_enable_output_b ("NORMAL" ),
- .clock_enable_output_a ("NORMAL" ),
- .wrcontrol_aclr_a ("NONE" ),
- .indata_aclr_a ("NONE" ),
- .address_aclr_a ("NONE" ),
- .outdata_aclr_a ("NONE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .operation_mode ("SINGLE_PORT" ),
- .intended_device_family ("CYCLONE IVE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .lpm_type ("altsyncram" ),
- .init_type ("unused" ),
- .ram_block_type ("AUTO" ),
- .numwords_b ( NUMWORDS ),
- .numwords_a ( NUMWORDS ),
- .widthad_b ( CFG_ABITS ),
- .width_b ( CFG_DBITS ),
- .widthad_a ( CFG_ABITS ),
- .width_a ( CFG_DBITS )
+ altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
+ .clock_enable_input_a ("ALTERNATE" ),
+ .clock_enable_output_b ("NORMAL" ),
+ .clock_enable_output_a ("NORMAL" ),
+ .wrcontrol_aclr_a ("NONE" ),
+ .indata_aclr_a ("NONE" ),
+ .address_aclr_a ("NONE" ),
+ .outdata_aclr_a ("NONE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .operation_mode ("SINGLE_PORT" ),
+ .intended_device_family ("CYCLONE IVE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .lpm_type ("altsyncram" ),
+ .init_type ("unused" ),
+ .ram_block_type ("AUTO" ),
+ .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
+ .power_up_uninitialized ("FALSE"),
+ .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
+ .width_byteena_a (1), // Forced value
+ .numwords_b ( NUMWORDS ),
+ .numwords_a ( NUMWORDS ),
+ .widthad_b ( CFG_ABITS ),
+ .width_b ( CFG_DBITS ),
+ .widthad_a ( CFG_ABITS ),
+ .width_a ( CFG_DBITS )