+ RTLIL::Module* box_module = design->module(cell->type);
+ if (box_module) {
+ auto jt = box_module->attributes.find("\\abc_scc_break");
+ if (jt != box_module->attributes.end()) {
+ auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string()));
+ log_assert(it != cell->connections_.end());
+ auto &c = *it;
+ SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string()));
+ Wire *w = b.wire;
+ log_assert(!w->port_output);
+ w->port_output = true;
+ w->set_bool_attribute("\\abc_scc_break");
+ w = module->wire(stringf("%s.abci", log_id(w->name)));
+ if (!w)
+ w = module->addWire(stringf("%s.abci", log_id(b.wire->name)), GetSize(b.wire));
+ log_assert(b.offset < GetSize(w));
+ w->port_input = true;
+ c.second = RTLIL::SigBit(w, b.offset);
+ }
+ }