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Rework RAM port for nMigen compliance
author
Jean THOMAS
<git0@pub.jeanthomas.me>
Mon, 8 Jun 2020 16:50:03 +0000
(18:50 +0200)
committer
Jean THOMAS
<git0@pub.jeanthomas.me>
Mon, 8 Jun 2020 16:50:03 +0000
(18:50 +0200)
gram/core/crossbar.py
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diff --git
a/gram/core/crossbar.py
b/gram/core/crossbar.py
index 1ca18e7dabc4bbad03674d6104a5621d16199994..c81abc77e1a597ccf7e4ec9d09e8c3912151d9e6 100644
(file)
--- a/
gram/core/crossbar.py
+++ b/
gram/core/crossbar.py
@@
-72,14
+72,13
@@
class gramCrossbar(Elaboratable):
self.rank_bits = log2_int(self.nranks, False)
self.masters = []
self.rank_bits = log2_int(self.nranks, False)
self.masters = []
+ self._pending_submodules = []
def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False):
def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False):
- if self.finalized:
- raise FinalizeError
-
if data_width is None:
# use internal data_width when no width adaptation is requested
data_width = self.controller.data_width
if data_width is None:
# use internal data_width when no width adaptation is requested
data_width = self.controller.data_width
+ print("data_width=", data_width)
# Crossbar port ----------------------------------------------------------------------------
port = gramNativePort(
# Crossbar port ----------------------------------------------------------------------------
port = gramNativePort(
@@
-98,7
+97,7
@@
class gramCrossbar(Elaboratable):
data_width = port.data_width,
clock_domain = clock_domain,
id = port.id)
data_width = port.data_width,
clock_domain = clock_domain,
id = port.id)
- self.
submodules += gramNativePortCDC(new_port, port
)
+ self.
_pending_submodules.append(gramNativePortCDC(new_port, port)
)
port = new_port
# Data width convertion --------------------------------------------------------------------
port = new_port
# Data width convertion --------------------------------------------------------------------
@@
-113,8
+112,8
@@
class gramCrossbar(Elaboratable):
data_width = data_width,
clock_domain = clock_domain,
id = port.id)
data_width = data_width,
clock_domain = clock_domain,
id = port.id)
- self.
submodules +=
ClockDomainsRenamer(clock_domain)(
-
LiteDRAMNativePortConverter(new_port, port, reverse
))
+ self.
_pending_submodules.append(
ClockDomainsRenamer(clock_domain)(
+
gramNativePortConverter(new_port, port, reverse)
))
port = new_port
return port
port = new_port
return port
@@
-122,6
+121,8
@@
class gramCrossbar(Elaboratable):
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
+ m.submodules += self._pending_submodules
+
controller = self.controller
nmasters = len(self.masters)
controller = self.controller
nmasters = len(self.masters)
@@
-203,7
+204,7
@@
class gramCrossbar(Elaboratable):
]
for nm, master in enumerate(self.masters):
with m.Case(2**nm):
]
for nm, master in enumerate(self.masters):
with m.Case(2**nm):
- m.d.comb = [
+ m.d.comb
+
= [
controller.wdata.eq(master.wdata.data),
controller.wdata_we.eq(master.wdata.we),
]
controller.wdata.eq(master.wdata.data),
controller.wdata_we.eq(master.wdata.we),
]