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shregmap -tech xilinx to delete $shiftx for var length SRL
author
Eddie Hung
<eddieh@ece.ubc.ca>
Tue, 19 Mar 2019 22:05:08 +0000
(15:05 -0700)
committer
Eddie Hung
<eddieh@ece.ubc.ca>
Tue, 19 Mar 2019 22:05:08 +0000
(15:05 -0700)
passes/techmap/shregmap.cc
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diff --git
a/passes/techmap/shregmap.cc
b/passes/techmap/shregmap.cc
index 3b3170e0491829331273e3db943fbbde21d46285..bd537e7c2c68f08df7c17a9936d4d6e4e24c58a8 100644
(file)
--- a/
passes/techmap/shregmap.cc
+++ b/
passes/techmap/shregmap.cc
@@
-187,19
+187,12
@@
struct ShregmapTechXilinx7 : ShregmapTech
if (it == sigbit_to_shiftx_offset.end())
return true;
if (it == sigbit_to_shiftx_offset.end())
return true;
- auto cell_q = cell->getPort("\\Q");
- log_assert(cell_q.is_bit());
-
Cell* shiftx = it->second.first;
Cell* shiftx = it->second.first;
- // FIXME: Hack to ensure that $shiftx gets optimised away
- // Without this, Yosys will refuse to optimise away a $shiftx
- // where \\A 's width is not perfectly \\B_WIDTH ** 2
- // See YosysHQ/yosys#878
- auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int();
- shiftx->setPort("\\A", cell_q.repeat(1 << shiftx_bwidth));
- shiftx->setParam("\\A_WIDTH", 1 << shiftx_bwidth);
cell->setPort("\\L", shiftx->getPort("\\B"));
cell->setPort("\\L", shiftx->getPort("\\B"));
+ cell->setPort("\\Q", shiftx->getPort("\\Y"));
+
+ cell->module->remove(shiftx);
return true;
}
return true;
}