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rename substep to ssubstep, add dsubstep to SVP64State
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 20 Jul 2022 19:20:06 +0000
(20:20 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 20 Jul 2022 19:20:06 +0000
(20:20 +0100)
src/openpower/decoder/isa/caller.py
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|
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src/openpower/decoder/isa/svstate.py
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src/openpower/decoder/power_decoder2.py
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src/openpower/sv/svstate.py
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diff --git
a/src/openpower/decoder/isa/caller.py
b/src/openpower/decoder/isa/caller.py
index 73fbecf334e25cf9d9ab02b3dfa1d099c2b01ba9..6b89ea2c850e3ab80095eeedf8ac2d1fa8b5c584 100644
(file)
--- a/
src/openpower/decoder/isa/caller.py
+++ b/
src/openpower/decoder/isa/caller.py
@@
-1142,7
+1142,7
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
in the class for later use. this to avoid problems with yield
"""
# go through all iterators in lock-step, advance to next remap_idx
in the class for later use. this to avoid problems with yield
"""
# go through all iterators in lock-step, advance to next remap_idx
- srcstep, dststep, substep = self.get_src_dststeps()
+ srcstep, dststep, s
s
ubstep = self.get_src_dststeps()
# get four SVSHAPEs. here we are hard-coding
SVSHAPE0 = self.spr['SVSHAPE0']
SVSHAPE1 = self.spr['SVSHAPE1']
# get four SVSHAPEs. here we are hard-coding
SVSHAPE0 = self.spr['SVSHAPE0']
SVSHAPE1 = self.spr['SVSHAPE1']
@@
-1294,7
+1294,7
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
self.update_nia()
self.update_pc_next()
return
self.update_nia()
self.update_pc_next()
return
- srcstep, dststep, substep = self.get_src_dststeps()
+ srcstep, dststep, s
s
ubstep = self.get_src_dststeps()
pred_dst_zero = self.pred_dst_zero
pred_src_zero = self.pred_src_zero
vl = self.svstate.vl
pred_dst_zero = self.pred_dst_zero
pred_src_zero = self.pred_src_zero
vl = self.svstate.vl
@@
-1472,11
+1472,11
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
offsmul = yield self.dec2.in1_step
log("D-field REMAP src", imm, offsmul)
else:
offsmul = yield self.dec2.in1_step
log("D-field REMAP src", imm, offsmul)
else:
- offsmul = (srcstep * (subvl+1)) + substep
+ offsmul = (srcstep * (subvl+1)) + s
s
ubstep
log("D-field src", imm, offsmul)
elif op == MicrOp.OP_STORE.value:
# XXX NOTE! no bit-reversed STORE! this should not ever be used
log("D-field src", imm, offsmul)
elif op == MicrOp.OP_STORE.value:
# XXX NOTE! no bit-reversed STORE! this should not ever be used
- offsmul = (dststep * (subvl+1)) + substep
+ offsmul = (dststep * (subvl+1)) + s
s
ubstep
log("D-field dst", imm, offsmul)
# bit-reverse mode, rev already done through get_src_dst_steps()
if ldstmode == SVP64LDSTmode.SHIFT.value:
log("D-field dst", imm, offsmul)
# bit-reverse mode, rev already done through get_src_dst_steps()
if ldstmode == SVP64LDSTmode.SHIFT.value:
@@
-1651,13
+1651,13
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
log("SVSTATE_NEXT: post-inc")
# use actual src/dst-step here to check end, do NOT
# use bit-reversed version
log("SVSTATE_NEXT: post-inc")
# use actual src/dst-step here to check end, do NOT
# use bit-reversed version
- srcstep, dststep, substep = \
- self.new_srcstep, self.new_dststep, self.new_substep
+ srcstep, dststep, s
s
ubstep = \
+ self.new_srcstep, self.new_dststep, self.new_s
s
ubstep
remaps = self.get_remap_indices()
remap_idxs = self.remap_idxs
vl = self.svstate.vl
subvl = yield self.dec2.rm_dec.rm_in.subvl
remaps = self.get_remap_indices()
remap_idxs = self.remap_idxs
vl = self.svstate.vl
subvl = yield self.dec2.rm_dec.rm_in.subvl
- end_sub = substep == subvl
+ end_sub = s
s
ubstep == subvl
end_src = srcstep == vl-1
end_dst = dststep == vl-1
if self.allow_next_step_inc != 2:
end_src = srcstep == vl-1
end_dst = dststep == vl-1
if self.allow_next_step_inc != 2:
@@
-1728,13
+1728,13
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
subvl = yield self.dec2.rm_dec.rm_in.subvl
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
subvl = yield self.dec2.rm_dec.rm_in.subvl
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
- s
ubstep = self.svstate.
substep
+ s
substep = self.svstate.s
substep
sv_a_nz = yield self.dec2.sv_a_nz
fft_mode = yield self.dec2.use_svp64_fft
in1 = yield self.dec2.e.read_reg1.data
sv_a_nz = yield self.dec2.sv_a_nz
fft_mode = yield self.dec2.use_svp64_fft
in1 = yield self.dec2.e.read_reg1.data
- log("SVP64: VL, subvl, srcstep, dststep, substep, sv_a_nz, "
+ log("SVP64: VL, subvl, srcstep, dststep, s
s
ubstep, sv_a_nz, "
"in1 fft, svp64",
"in1 fft, svp64",
- vl, subvl, srcstep, dststep, substep, sv_a_nz, in1, fft_mode,
+ vl, subvl, srcstep, dststep, s
s
ubstep, sv_a_nz, in1, fft_mode,
self.is_svp64_mode)
# get predicate mask (all 64 bits)
self.is_svp64_mode)
# get predicate mask (all 64 bits)
@@
-1755,8
+1755,8
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
if sv_ptype == SVPtype.P2.value:
srcmask = get_predcr(self.crl, srcpred, vl)
srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
if sv_ptype == SVPtype.P2.value:
srcmask = get_predcr(self.crl, srcpred, vl)
- # work out if the substeps are completed
- end_sub = substep == subvl
+ # work out if the s
s
ubsteps are completed
+ end_sub = s
s
ubstep == subvl
log(" pmode", pmode)
log(" reverse", reverse_gear)
log(" ptype", sv_ptype)
log(" pmode", pmode)
log(" reverse", reverse_gear)
log(" ptype", sv_ptype)
@@
-1781,10
+1781,10
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
while (((1 << dststep) & dstmask) == 0) and (dststep != vl):
log(" skip", bin(1 << dststep))
dststep += 1
while (((1 << dststep) & dstmask) == 0) and (dststep != vl):
log(" skip", bin(1 << dststep))
dststep += 1
- # and reset substep back to zero
- substep = 0
+ # and reset s
s
ubstep back to zero
+ s
s
ubstep = 0
else:
else:
- s
ubstep += 1 # advance
substep
+ s
substep += 1 # advance s
substep
# now work out if the relevant mask bits require zeroing
if pred_dst_zero:
# now work out if the relevant mask bits require zeroing
if pred_dst_zero:
@@
-1793,38
+1793,38
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
pred_src_zero = ((1 << srcstep) & srcmask) == 0
# store new srcstep / dststep
pred_src_zero = ((1 << srcstep) & srcmask) == 0
# store new srcstep / dststep
- self.new_srcstep, self.new_dststep, self.new_substep = \
- (srcstep, dststep, substep)
+ self.new_srcstep, self.new_dststep, self.new_s
s
ubstep = \
+ (srcstep, dststep, s
s
ubstep)
self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
log(" new srcstep", srcstep)
log(" new dststep", dststep)
self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
log(" new srcstep", srcstep)
log(" new dststep", dststep)
- log(" new s
ubstep",
substep)
+ log(" new s
substep", s
substep)
def get_src_dststeps(self):
def get_src_dststeps(self):
- """gets srcstep, dststep, and substep
+ """gets srcstep, dststep, and s
s
ubstep
"""
"""
- return self.new_srcstep, self.new_dststep, self.new_substep
+ return self.new_srcstep, self.new_dststep, self.new_s
s
ubstep
def update_new_svstate_steps(self):
# note, do not get the bit-reversed srcstep here!
def update_new_svstate_steps(self):
# note, do not get the bit-reversed srcstep here!
- srcstep, dststep, substep = \
- self.new_srcstep, self.new_dststep, self.new_substep
+ srcstep, dststep, s
s
ubstep = \
+ self.new_srcstep, self.new_dststep, self.new_s
s
ubstep
# update SVSTATE with new srcstep
self.svstate.srcstep = srcstep
self.svstate.dststep = dststep
# update SVSTATE with new srcstep
self.svstate.srcstep = srcstep
self.svstate.dststep = dststep
- self.svstate.s
ubstep =
substep
+ self.svstate.s
substep = s
substep
self.namespace['SVSTATE'] = self.svstate
yield self.dec2.state.svstate.eq(self.svstate.value)
yield Settle() # let decoder update
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
self.namespace['SVSTATE'] = self.svstate
yield self.dec2.state.svstate.eq(self.svstate.value)
yield Settle() # let decoder update
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
- s
ubstep = self.svstate.
substep
+ s
substep = self.svstate.s
substep
vl = self.svstate.vl
subvl = yield self.dec2.rm_dec.rm_in.subvl
log(" srcstep", srcstep)
log(" dststep", dststep)
vl = self.svstate.vl
subvl = yield self.dec2.rm_dec.rm_in.subvl
log(" srcstep", srcstep)
log(" dststep", dststep)
- log(" s
ubstep",
substep)
+ log(" s
substep", s
substep)
log(" vl", vl)
log(" subvl", subvl)
log(" vl", vl)
log(" subvl", subvl)
@@
-1848,7
+1848,7
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
mvl = self.svstate.maxvl
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
mvl = self.svstate.maxvl
srcstep = self.svstate.srcstep
dststep = self.svstate.dststep
- s
ubstep = self.svstate.
substep
+ s
substep = self.svstate.s
substep
rm_mode = yield self.dec2.rm_dec.mode
reverse_gear = yield self.dec2.rm_dec.reverse_gear
sv_ptype = yield self.dec2.dec.op.SV_Ptype
rm_mode = yield self.dec2.rm_dec.mode
reverse_gear = yield self.dec2.rm_dec.reverse_gear
sv_ptype = yield self.dec2.dec.op.SV_Ptype
@@
-1859,7
+1859,7
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
log(" rm.subvl", subvl)
log(" svstate.srcstep", srcstep)
log(" svstate.dststep", dststep)
log(" rm.subvl", subvl)
log(" svstate.srcstep", srcstep)
log(" svstate.dststep", dststep)
- log(" svstate.s
ubstep",
substep)
+ log(" svstate.s
substep", s
substep)
log(" mode", rm_mode)
log(" reverse", reverse_gear)
log(" out_vec", out_vec)
log(" mode", rm_mode)
log(" reverse", reverse_gear)
log(" out_vec", out_vec)
@@
-1901,16
+1901,16
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
def advance_svstate_steps(self, end_src=False, end_dst=False):
subvl = yield self.dec2.rm_dec.rm_in.subvl
def advance_svstate_steps(self, end_src=False, end_dst=False):
subvl = yield self.dec2.rm_dec.rm_in.subvl
- s
ubstep = self.svstate.
substep
- end_sub = substep == subvl
+ s
substep = self.svstate.s
substep
+ end_sub = s
s
ubstep == subvl
if end_sub:
if not end_src:
self.svstate.srcstep += SelectableInt(1, 7)
if not end_dst:
self.svstate.dststep += SelectableInt(1, 7)
if end_sub:
if not end_src:
self.svstate.srcstep += SelectableInt(1, 7)
if not end_dst:
self.svstate.dststep += SelectableInt(1, 7)
- self.svstate.substep = SelectableInt(0, 2)
+ self.svstate.s
s
ubstep = SelectableInt(0, 2)
else:
else:
- self.svstate.s
ubstep += SelectableInt(1, 2) # advance
substep
+ self.svstate.s
substep += SelectableInt(1, 2) # advance s
substep
def update_pc_next(self):
# UPDATE program counter
def update_pc_next(self):
# UPDATE program counter
@@
-1923,7
+1923,7
@@
class ISACaller(ISACallerHelper, ISAFPHelpers):
def svp64_reset_loop(self):
self.svstate.srcstep = 0
self.svstate.dststep = 0
def svp64_reset_loop(self):
self.svstate.srcstep = 0
self.svstate.dststep = 0
- self.svstate.substep = 0
+ self.svstate.s
s
ubstep = 0
log(" svstate.srcstep loop end (PC to update)")
self.namespace['SVSTATE'] = self.svstate
log(" svstate.srcstep loop end (PC to update)")
self.namespace['SVSTATE'] = self.svstate
diff --git
a/src/openpower/decoder/isa/svstate.py
b/src/openpower/decoder/isa/svstate.py
index 86b17f6b2b5a9bce3e3b5def695f89876504085c..9b8c89be9cbf5227dde3f208ed645e8020b2a05d 100644
(file)
--- a/
src/openpower/decoder/isa/svstate.py
+++ b/
src/openpower/decoder/isa/svstate.py
@@
-56,12
+56,20
@@
class SVP64State(SelectableInt):
self.fsi['srcstep'].eq(value)
@property
self.fsi['srcstep'].eq(value)
@property
- def substep(self):
- return self.fsi['substep'].asint(msb0=True)
+ def
d
substep(self):
+ return self.fsi['
d
substep'].asint(msb0=True)
- @substep.setter
- def substep(self, value):
- self.fsi['substep'].eq(value)
+ @dsubstep.setter
+ def dsubstep(self, value):
+ self.fsi['dsubstep'].eq(value)
+
+ @property
+ def ssubstep(self):
+ return self.fsi['ssubstep'].asint(msb0=True)
+
+ @ssubstep.setter
+ def ssubstep(self, value):
+ self.fsi['ssubstep'].eq(value)
@property
def subvl(self):
@property
def subvl(self):
diff --git
a/src/openpower/decoder/power_decoder2.py
b/src/openpower/decoder/power_decoder2.py
index 155627834417348776fbde03d22066ae0b8ecf39..52ae69cecfc41cfe5ce739ccd53c6ebeec0c9a2d 100644
(file)
--- a/
src/openpower/decoder/power_decoder2.py
+++ b/
src/openpower/decoder/power_decoder2.py
@@
-1306,15
+1306,15
@@
class PowerDecode2(PowerDecodeSubset):
# get SVSTATE srcstep (TODO: elwidth etc.) needed below
vl = Signal.like(self.state.svstate.vl)
# get SVSTATE srcstep (TODO: elwidth etc.) needed below
vl = Signal.like(self.state.svstate.vl)
- subvl = Signal.like(self.
state.svstate
.subvl)
+ subvl = Signal.like(self.
rm_dec.rm_in
.subvl)
srcstep = Signal.like(self.state.svstate.srcstep)
dststep = Signal.like(self.state.svstate.dststep)
srcstep = Signal.like(self.state.svstate.srcstep)
dststep = Signal.like(self.state.svstate.dststep)
- s
ubstep = Signal.like(self.state.svstate.
substep)
+ s
substep = Signal.like(self.state.svstate.s
substep)
comb += vl.eq(self.state.svstate.vl)
comb += subvl.eq(self.rm_dec.rm_in.subvl)
comb += srcstep.eq(self.state.svstate.srcstep)
comb += dststep.eq(self.state.svstate.dststep)
comb += vl.eq(self.state.svstate.vl)
comb += subvl.eq(self.rm_dec.rm_in.subvl)
comb += srcstep.eq(self.state.svstate.srcstep)
comb += dststep.eq(self.state.svstate.dststep)
- comb += s
ubstep.eq(self.state.svstate.
substep)
+ comb += s
substep.eq(self.state.svstate.s
substep)
in1_step, in2_step = self.in1_step, self.in2_step
in3_step = self.in3_step
in1_step, in2_step = self.in1_step, self.in2_step
in3_step = self.in3_step
@@
-1357,9
+1357,9
@@
class PowerDecode2(PowerDecodeSubset):
selectstep = dststep if out else srcstep
step = Signal(7, name="step_%s" % rname.lower())
with m.If(self.remap_active[i]):
selectstep = dststep if out else srcstep
step = Signal(7, name="step_%s" % rname.lower())
with m.If(self.remap_active[i]):
- comb += step.eq((remapstep*(subvl+1))+substep)
+ comb += step.eq((remapstep*(subvl+1))+s
s
ubstep)
with m.Else():
with m.Else():
- comb += step.eq((selectstep*(subvl+1))+substep)
+ comb += step.eq((selectstep*(subvl+1))+s
s
ubstep)
# reverse gear goes the opposite way
with m.If(self.rm_dec.reverse_gear):
comb += to_reg.data.eq(offs+svdec.reg_out+(vmax-1-step))
# reverse gear goes the opposite way
with m.If(self.rm_dec.reverse_gear):
comb += to_reg.data.eq(offs+svdec.reg_out+(vmax-1-step))
diff --git
a/src/openpower/sv/svstate.py
b/src/openpower/sv/svstate.py
index da1b5fac10cf966c069e303f23d86ca112cb00ae..46445845dd06852162972992edd76fbaaba7daf3 100644
(file)
--- a/
src/openpower/sv/svstate.py
+++ b/
src/openpower/sv/svstate.py
@@
-11,8
+11,8
@@
https://libre-soc.org/openpower/sv/sprs/
| 7:13 | vl | Vector Length |
| 14:20 | srcstep | for srcstep = 0..VL-1 |
| 21:27 | dststep | for dststep = 0..VL-1 |
| 7:13 | vl | Vector Length |
| 14:20 | srcstep | for srcstep = 0..VL-1 |
| 21:27 | dststep | for dststep = 0..VL-1 |
-| 28:29 |
subvl | Sub-vector length
|
-| 30:31 | s
ubstep | for
substep = 0..SUBVL-1 |
+| 28:29 |
dsubstep | for dsubstep = 0..SUBVL-1
|
+| 30:31 | s
substep | for s
substep = 0..SUBVL-1 |
| 32:33 | mi0 | REMAP RA SVSHAPE0-3 |
| 34:35 | mi1 | REMAP RB SVSHAPE0-3 |
| 36:37 | mi2 | REMAP RC SVSHAPE0-3 |
| 32:33 | mi0 | REMAP RA SVSHAPE0-3 |
| 34:35 | mi1 | REMAP RB SVSHAPE0-3 |
| 36:37 | mi2 | REMAP RC SVSHAPE0-3 |
@@
-39,8
+39,8
@@
class SVSTATERec(Record):
("mi2", 2),
("mi1", 2),
("mi0", 2),
("mi2", 2),
("mi1", 2),
("mi0", 2),
- ("substep", 2),
- ("
subvl
", 2),
+ ("s
s
ubstep", 2),
+ ("
dsunstep
", 2),
("dststep", 7),
("srcstep", 7),
("vl", 7),
("dststep", 7),
("srcstep", 7),
("vl", 7),