- SV64P_PID_SIZE, SVP64RMFields,
- SVP64RM_EXTRA2_SPEC_SIZE,
- SVP64RM_EXTRA3_SPEC_SIZE,
- SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
- SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
- SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
- SVP64RM_ELWIDTH_SIZE)
+ SV64P_PID_SIZE, SVP64RMFields,
+ SVP64RM_EXTRA2_SPEC_SIZE,
+ SVP64RM_EXTRA3_SPEC_SIZE,
+ SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
+ SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
+ SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
+ SVP64RM_ELWIDTH_SIZE)
from openpower.decoder.pseudo.pagereader import ISA
from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
from openpower.decoder.selectable_int import SelectableInt
from openpower.decoder.pseudo.pagereader import ISA
from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
from openpower.decoder.selectable_int import SelectableInt
- pmap = { # integer
- '1<<r3': (0, 0b001),
- 'r3' : (0, 0b010),
- '~r3' : (0, 0b011),
- 'r10' : (0, 0b100),
- '~r10' : (0, 0b101),
- 'r30' : (0, 0b110),
- '~r30' : (0, 0b111),
- # CR
- 'lt' : (1, 0b000),
- 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
- 'gt' : (1, 0b010),
- 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
- 'eq' : (1, 0b100),
- 'ne' : (1, 0b101),
- 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
- 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
- }
+ pmap = { # integer
+ '1<<r3': (0, 0b001),
+ 'r3': (0, 0b010),
+ '~r3': (0, 0b011),
+ 'r10': (0, 0b100),
+ '~r10': (0, 0b101),
+ 'r30': (0, 0b110),
+ '~r30': (0, 0b111),
+ # CR
+ 'lt': (1, 0b000),
+ 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
+ 'gt': (1, 0b010),
+ 'ng': (1, 0b011), 'le': (1, 0b011), # same value
+ 'eq': (1, 0b100),
+ 'ne': (1, 0b101),
+ 'so': (1, 0b110), 'un': (1, 0b110), # same value
+ 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
+ }
- pmap = { # TODO: double-check that these are the same as Branch BO
- 'lt' : 0b000,
- 'nl' : 0b001, 'ge' : 0b001, # same value
- 'gt' : 0b010,
- 'ng' : 0b011, 'le' : 0b011, # same value
- 'eq' : 0b100,
- 'ne' : 0b101,
- 'so' : 0b110, 'un' : 0b110, # same value
- 'ns' : 0b111, 'nu' : 0b111, # same value
- }
+ pmap = { # TODO: double-check that these are the same as Branch BO
+ 'lt': 0b000,
+ 'nl': 0b001, 'ge': 0b001, # same value
+ 'gt': 0b010,
+ 'ng': 0b011, 'le': 0b011, # same value
+ 'eq': 0b100,
+ 'ne': 0b101,
+ 'so': 0b110, 'un': 0b110, # same value
+ 'ns': 0b111, 'nu': 0b111, # same value
+ }
# sigh have to do setvl here manually for now...
# note the subtract one from SVi.
if opcode in ["setvl", "setvl."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
# sigh have to do setvl here manually for now...
# note the subtract one from SVi.
if opcode in ["setvl", "setvl."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
- insn |= fields[0] << (31-10) # RT , bits 6-10
- insn |= fields[1] << (31-15) # RA , bits 11-15
- insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
- insn |= fields[3] << (31-25) # ms , bit 25
- insn |= fields[4] << (31-24) # vs , bit 24
- insn |= fields[5] << (31-23) # vf , bit 23
- insn |= 0b00000 << (31-30) # XO , bits 26..30
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= fields[1] << (31-15) # RA , bits 11-15
+ insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
+ insn |= fields[3] << (31-25) # ms , bit 25
+ insn |= fields[4] << (31-24) # vs , bit 24
+ insn |= fields[5] << (31-23) # vf , bit 23
+ insn |= 0b00000 << (31-30) # XO , bits 26..30
if opcode in ["svstep", "svstep."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
if opcode in ["svstep", "svstep."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
- insn |= fields[0] << (31-10) # RT , bits 6-10
- insn |= (fields[1]-1) << (31-22) # SVi , bits 16-22
- insn |= fields[2] << (31-25) # vf , bit 25
- insn |= 0b00011 << (31-30) # XO , bits 26..30
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= (fields[1]-1) << (31-22) # SVi , bits 16-22
+ insn |= fields[2] << (31-25) # vf , bit 25
+ insn |= 0b00011 << (31-30) # XO , bits 26..30
- insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
- insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
- insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
- insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
- insn |= (fields[4]) << (31-25) # vf , bits 25
- insn |= 0b00001 << (31-30) # XO , bits 26..30
+ insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
+ insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
+ insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
+ insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
+ insn |= (fields[4]) << (31-25) # vf , bits 25
+ insn |= 0b00001 << (31-30) # XO , bits 26..30
- insn |= fields[0] << (31-10) # SVme , bits 6-10
- insn |= fields[1] << (31-12) # mi0 , bits 11-12
- insn |= fields[2] << (31-14) # mi1 , bits 13-14
- insn |= fields[3] << (31-16) # mi2 , bits 15-16
- insn |= fields[4] << (31-18) # m00 , bits 17-18
- insn |= fields[5] << (31-20) # m01 , bits 19-20
- insn |= fields[6] << (31-21) # m01 , bit 21
- insn |= 0b00010 << (31-30) # XO , bits 26..30
+ insn |= fields[0] << (31-10) # SVme , bits 6-10
+ insn |= fields[1] << (31-12) # mi0 , bits 11-12
+ insn |= fields[2] << (31-14) # mi1 , bits 13-14
+ insn |= fields[3] << (31-16) # mi2 , bits 15-16
+ insn |= fields[4] << (31-18) # m00 , bits 17-18
+ insn |= fields[5] << (31-20) # m01 , bits 19-20
+ insn |= fields[6] << (31-21) # m01 , bit 21
+ insn |= 0b00010 << (31-30) # XO , bits 26..30
- insn = 59 << (31-5) # opcode 59, bits 0-5
- insn |= fields[0] << (31-10) # RT , bits 6-10
- insn |= fields[1] << (31-20) # RB , bits 16-20
- insn |= 0b1000001110 << (31-30) # XO , bits 21..30
+ insn = 59 << (31-5) # opcode 59, bits 0-5
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= fields[1] << (31-20) # RB , bits 16-20
+ insn |= 0b1000001110 << (31-30) # XO , bits 21..30
- insn = 59 << (31-5) # opcode 59, bits 0-5
- insn |= fields[0] << (31-10) # RT , bits 6-10
- insn |= fields[1] << (31-20) # RB , bits 16-20
- insn |= 0b1000101110 << (31-30) # XO , bits 21..30
+ insn = 59 << (31-5) # opcode 59, bits 0-5
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= fields[1] << (31-20) # RB , bits 16-20
+ insn |= 0b1000101110 << (31-30) # XO , bits 21..30
- RC = int(newfields.pop(2)) # better be an integer number!
- if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
- immed = (immed & 0b11111111111) | (RC<<11)
- if immed & (1<<15): # should be negative
- immed -= 1<<16
- if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
- immed = (immed & 0b111111111) | (RC<<9)
- if immed & (1<<13): # should be negative
- immed -= 1<<14
+ RC = int(newfields.pop(2)) # better be an integer number!
+ if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
+ immed = (immed & 0b11111111111) | (RC << 11)
+ if immed & (1 << 15): # should be negative
+ immed -= 1 << 16
+ if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
+ immed = (immed & 0b111111111) | (RC << 9)
+ if immed & (1 << 13): # should be negative
+ immed -= 1 << 14
- log ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
- log ("v3.0B regs", opcode, v30b_regs)
- log ("RM", rm)
+ log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
+ log("v3.0B regs", opcode, v30b_regs)
+ log("RM", rm)
- log ("EXTRA field index, src", svp64_src)
- log ("EXTRA field index, dest", svp64_dest)
+ log("EXTRA field index, src", svp64_src)
+ log("EXTRA field index, dest", svp64_dest)
# okaaay now we identify the field value (opcode N,N,N) with
# the pseudo-code info (opcode RT, RA, RB)
assert len(fields) == len(v30b_regs), \
"length of fields %s must match insn `%s` fields %s" % \
# okaaay now we identify the field value (opcode N,N,N) with
# the pseudo-code info (opcode RT, RA, RB)
assert len(fields) == len(v30b_regs), \
"length of fields %s must match insn `%s` fields %s" % \
for idx, (field, regname) in enumerate(opregfields):
imm, regname = decode_imm(regname)
rtype = get_regtype(regname)
for idx, (field, regname) in enumerate(opregfields):
imm, regname = decode_imm(regname)
rtype = get_regtype(regname)
if rtype is None:
# probably an immediate field, append it straight
extras[('imm', idx, False)] = (idx, field, None, None, None)
continue
extra = svp64_src.get(regname, None)
if extra is not None:
if rtype is None:
# probably an immediate field, append it straight
extras[('imm', idx, False)] = (idx, field, None, None, None)
continue
extra = svp64_src.get(regname, None)
if extra is not None:
dextra = ('d', dextra, is_a_duplicate)
extras[dextra] = (idx, field, regname, rtype, imm)
dextra = ('d', dextra, is_a_duplicate)
extras[dextra] = (idx, field, regname, rtype, imm)
- log (" ", extra_idx, rname, rtype,
- regmode, iname, field, end=" ")
+ log(" ", extra_idx, rname, rtype,
+ regmode, iname, field, end=" ")
# all good: encode as scalar
sv_extra = sv_extra & 0b01
else:
# range is CR0-CR127 in increments of 16
assert sv_extra & 0b111 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b01
else:
# range is CR0-CR127 in increments of 16
assert sv_extra & 0b111 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b11
else:
# range is CR0-CR127 in increments of 8
assert sv_extra & 0b11 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b11
else:
# range is CR0-CR127 in increments of 8
assert sv_extra & 0b11 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b01
else:
# range is CR0-CR127 in increments of 16
assert sv_extra & 0b111 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b01
else:
# range is CR0-CR127 in increments of 16
assert sv_extra & 0b111 == 0, \
"vector CR %s cannot fit into EXTRA2 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b11
else:
# range is CR0-CR127 in increments of 8
assert sv_extra & 0b11 == 0, \
"vector CR %s cannot fit into EXTRA3 %s" % \
# all good: encode as scalar
sv_extra = sv_extra & 0b11
else:
# range is CR0-CR127 in increments of 8
assert sv_extra & 0b11 == 0, \
"vector CR %s cannot fit into EXTRA3 %s" % \
# all good: encode as vector (bit 3 set)
sv_extra = 0b100 | (sv_extra >> 2)
# reconstruct the actual 5-bit CR field
field = (field << 2) | cr_subfield
else:
# all good: encode as vector (bit 3 set)
sv_extra = 0b100 | (sv_extra >> 2)
# reconstruct the actual 5-bit CR field
field = (field << 2) | cr_subfield
else:
extras[extra_idx] = sv_extra
# append altered field value to v3.0b, differs for LDST
# note that duplicates are skipped e.g. EXTRA2 contains
# *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
srcdest, idx, duplicate = extra_idx
extras[extra_idx] = sv_extra
# append altered field value to v3.0b, differs for LDST
# note that duplicates are skipped e.g. EXTRA2 contains
# *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
srcdest, idx, duplicate = extra_idx
# rright. now we have all the info. start creating SVP64 RM
svp64_rm = SVP64RMFields()
# begin with EXTRA fields
for idx, sv_extra in extras.items():
# rright. now we have all the info. start creating SVP64 RM
svp64_rm = SVP64RMFields()
# begin with EXTRA fields
for idx, sv_extra in extras.items():
- "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
- "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
- "lfs", "lfsx", "lfsu", "lfsux", # FP load single
- "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
- "lha", "lharx", "lhau", "lhaux", "lhax", # load half
- "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
- "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
- "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
+ "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
+ "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
+ "lfs", "lfsx", "lfsu", "lfsux", # FP load single
+ "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
+ "lha", "lharx", "lhau", "lhaux", "lhax", # load half
+ "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
+ "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
+ "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
- "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
- "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
- "stfs", "stfsx", "stfsu", "stfux", # FP store single
- "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
- "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
- "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
+ "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
+ "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
+ "stfs", "stfsx", "stfsu", "stfux", # FP store single
+ "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
+ "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
+ "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
assert rc_mode, "CRM only allowed when Rc=1"
# bit of weird encoding to jam zero-pred or SVM mode in.
# SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
if subvl == 0:
assert rc_mode, "CRM only allowed when Rc=1"
# bit of weird encoding to jam zero-pred or SVM mode in.
# SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
if subvl == 0:
- mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
- mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
- assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
+ mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
+ mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+ assert rc_mode == False, "ffirst RC1 only possible when Rc=0"
- mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
- mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
- mode |= (0b1<<SVP64MODE.INV) # ... with inversion
- assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
+ mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
+ mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+ mode |= (0b1 << SVP64MODE.INV) # ... with inversion
+ assert rc_mode == False, "ffirst RC1 only possible when Rc=0"
######################################
# "predicate-result" modes. err... code-duplication from ffirst
elif sv_mode == 0b11:
assert src_zero == 0, "dest-zero not allowed in predresult mode"
if predresult == 'RC1':
######################################
# "predicate-result" modes. err... code-duplication from ffirst
elif sv_mode == 0b11:
assert src_zero == 0, "dest-zero not allowed in predresult mode"
if predresult == 'RC1':
- mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
- mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
- assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
+ mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+ assert rc_mode == False, "pr-mode RC1 only possible when Rc=0"
- mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
- mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
- mode |= (0b1<<SVP64MODE.INV) # ... with inversion
- assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
+ mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+ mode |= (0b1 << SVP64MODE.INV) # ... with inversion
+ assert rc_mode == False, "pr-mode RC1 only possible when Rc=0"
- log ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
- log (" mmode 0 :", bin(mmode))
- log (" pmask 1-3 :", bin(pmask))
- log (" dstwid 4-5 :", bin(destwid))
- log (" srcwid 6-7 :", bin(srcwid))
- log (" subvl 8-9 :", bin(subvl))
- log (" mode 19-23:", bin(mode))
- offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
+ log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
+ log(" mmode 0 :", bin(mmode))
+ log(" pmask 1-3 :", bin(pmask))
+ log(" dstwid 4-5 :", bin(destwid))
+ log(" srcwid 6-7 :", bin(srcwid))
+ log(" subvl 8-9 :", bin(subvl))
+ log(" mode 19-23:", bin(mode))
+ offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
- opcode |= int(v30b_newfields[0]) << (32-11) # FRT
- opcode |= int(v30b_newfields[1]) << (32-16) # FRA
- opcode |= int(v30b_newfields[2]) << (32-21) # FRB
- opcode |= int(v30b_newfields[3]) << (32-26) # FRC
+ opcode |= int(v30b_newfields[0]) << (32-11) # FRT
+ opcode |= int(v30b_newfields[1]) << (32-16) # FRA
+ opcode |= int(v30b_newfields[2]) << (32-21) # FRB
+ opcode |= int(v30b_newfields[3]) << (32-26) # FRC
- opcode |= int(v30b_newfields[0]) << (32-11) # FRT
- opcode |= int(v30b_newfields[1]) << (32-16) # FRA
- opcode |= int(v30b_newfields[2]) << (32-21) # FRB
- opcode |= int(v30b_newfields[3]) << (32-26) # FRC
+ opcode |= int(v30b_newfields[0]) << (32-11) # FRT
+ opcode |= int(v30b_newfields[1]) << (32-16) # FRA
+ opcode |= int(v30b_newfields[2]) << (32-21) # FRB
+ opcode |= int(v30b_newfields[3]) << (32-26) # FRC
# sigh have to do svstep here manually for now...
elif opcode in ["svstep", "svstep."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
# sigh have to do svstep here manually for now...
elif opcode in ["svstep", "svstep."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
- insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
- insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
- insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
- insn |= 0b00011 << (31-30) # XO , bits 26..30
+ insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
+ insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
+ insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
+ insn |= 0b00011 << (31-30) # XO , bits 26..30
yield ".long 0x%x" % insn
elif v30b_op in ["setvl", "setvl."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
yield ".long 0x%x" % insn
elif v30b_op in ["setvl", "setvl."]:
insn = 22 << (31-5) # opcode 22, bits 0-5
fields = list(map(int, fields))
- insn |= fields[0] << (31-10) # RT , bits 6-10
- insn |= fields[1] << (31-15) # RA , bits 11-15
- insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
- insn |= fields[3] << (31-25) # ms , bit 25
- insn |= fields[4] << (31-24) # vs , bit 24
- insn |= fields[5] << (31-23) # vf , bit 23
- insn |= 0b00000 << (31-30) # XO , bits 26..30
+ insn |= fields[0] << (31-10) # RT , bits 6-10
+ insn |= fields[1] << (31-15) # RA , bits 11-15
+ insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
+ insn |= fields[3] << (31-25) # ms , bit 25
+ insn |= fields[4] << (31-24) # vs , bit 24
+ insn |= fields[5] << (31-23) # vf , bit 23
+ insn |= 0b00000 << (31-30) # XO , bits 26..30
- insn = 59 << (31-5) # opcode 59, bits 0-5
- insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
- insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
- insn |= 0b1000101110 << (31-30) # XO , bits 21..30
+ insn = 59 << (31-5) # opcode 59, bits 0-5
+ insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
+ insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
+ insn |= 0b1000101110 << (31-30) # XO , bits 21..30
- 'extsw 5, 3',
- 'sv.extsw 5, 3',
- 'sv.cmpi 5, 1, 3, 2',
- 'sv.setb 5, 31',
- 'sv.isel 64.v, 3, 2, 65.v',
- 'sv.setb/dm=r3/sm=1<<r3 5, 31',
- 'sv.setb/m=r3 5, 31',
- 'sv.setb/vec2 5, 31',
- 'sv.setb/sw=8/ew=16 5, 31',
- 'sv.extsw./ff=eq 5, 31',
- 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
- 'sv.extsw./pr=eq 5.v, 31',
- 'sv.add. 5.v, 2.v, 1.v',
- 'sv.add./m=r3 5.v, 2.v, 1.v',
- ]
+ 'extsw 5, 3',
+ 'sv.extsw 5, 3',
+ 'sv.cmpi 5, 1, 3, 2',
+ 'sv.setb 5, 31',
+ 'sv.isel 64.v, 3, 2, 65.v',
+ 'sv.setb/dm=r3/sm=1<<r3 5, 31',
+ 'sv.setb/m=r3 5, 31',
+ 'sv.setb/vec2 5, 31',
+ 'sv.setb/sw=8/ew=16 5, 31',
+ 'sv.extsw./ff=eq 5, 31',
+ 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
+ 'sv.extsw./pr=eq 5.v, 31',
+ 'sv.add. 5.v, 2.v, 1.v',
+ 'sv.add./m=r3 5.v, 2.v, 1.v',
+ ]
- 'sv.stw 5.v, 4(1.v)',
- 'sv.ld 5.v, 4(1.v)',
- 'setvl. 2, 3, 4, 0, 1, 1',
- 'sv.setvl. 2, 3, 4, 0, 1, 1',
- ]
+ 'sv.stw 5.v, 4(1.v)',
+ 'sv.ld 5.v, 4(1.v)',
+ 'setvl. 2, 3, 4, 0, 1, 1',
+ 'sv.setvl. 2, 3, 4, 0, 1, 1',
+ ]
- 'sv.addi win2.v, win.v, -1',
- 'sv.add./mrr 5.v, 2.v, 1.v',
- #'sv.lhzsh 5.v, 11(9.v), 15',
- #'sv.lwzsh 5.v, 11(9.v), 15',
- 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
+ 'sv.addi win2.v, win.v, -1',
+ 'sv.add./mrr 5.v, 2.v, 1.v',
+ #'sv.lhzsh 5.v, 11(9.v), 15',
+ #'sv.lwzsh 5.v, 11(9.v), 15',
+ 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
- #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
- #'sv.ffadds 0.v, 8.v, 4.v',
- 'svremap 11, 0, 1, 2, 3, 2, 1',
- 'svshape 8, 1, 1, 1, 0',
- 'svshape 8, 1, 1, 1, 1',
- ]
+ #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
+ #'sv.ffadds 0.v, 8.v, 4.v',
+ 'svremap 11, 0, 1, 2, 3, 2, 1',
+ 'svshape 8, 1, 1, 1, 0',
+ 'svshape 8, 1, 1, 1, 1',
+ ]
- #'sv.lfssh 4.v, 11(8.v), 15',
- #'sv.lwzsh 4.v, 11(8.v), 15',
- #'sv.svstep. 2.v, 4, 0',
- #'sv.fcfids. 48.v, 64.v',
- 'sv.fcoss. 80.v, 0.v',
- 'sv.fcoss. 20.v, 0.v',
- ]
+ #'sv.lfssh 4.v, 11(8.v), 15',
+ #'sv.lwzsh 4.v, 11(8.v), 15',
+ #'sv.svstep. 2.v, 4, 0',
+ #'sv.fcfids. 48.v, 64.v',
+ 'sv.fcoss. 80.v, 0.v',
+ 'sv.fcoss. 20.v, 0.v',
+ ]
lst = [
'sv.bc/all 3,12,192',
'sv.bclr/vsbi 3,81.v,192',
]
isa = SVP64Asm(lst, macros=macros)
lst = [
'sv.bc/all 3,12,192',
'sv.bclr/vsbi 3,81.v,192',
]
isa = SVP64Asm(lst, macros=macros)