projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
d4d6929
)
techmap before read
author
Eddie Hung
<eddie@fpgeh.com>
Wed, 21 Aug 2019 18:47:06 +0000
(11:47 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Wed, 21 Aug 2019 18:47:06 +0000
(11:47 -0700)
techlibs/xilinx/synth_xilinx.cc
patch
|
blob
|
history
diff --git
a/techlibs/xilinx/synth_xilinx.cc
b/techlibs/xilinx/synth_xilinx.cc
index 263788fecdd213e1872c977577200f5d8e34bb08..2181923150339f407bc7fcee49c288a3a0672bd7 100644
(file)
--- a/
techlibs/xilinx/synth_xilinx.cc
+++ b/
techlibs/xilinx/synth_xilinx.cc
@@
-390,8
+390,8
@@
struct SynthXilinxPass : public ScriptPass
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
- run("read_verilog -icells -lib +/xilinx/abc_model.v");
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+ run("read_verilog -icells -lib +/xilinx/abc_model.v");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else