drm-uapi: bump headers

Required updates from drm-next for changes in i965.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org

diff --git a/include/drm-uapi/README b/include/drm-uapi/README
index 53dd711dad52e7d923b0ce49f128a397da0726f0..7f63fb2038ba2e41081a3b7f2aa48bdd84e39ffd 100644 (file)
--- a/include/drm-uapi/README
+++ b/include/drm-uapi/README
@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
 
 The last update was done at the following kernel commit :
 
 
 The last update was done at the following kernel commit :
 

-commit ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
-Merge: 2c1c55cb75a9 010d118c2061
+commit 78230c46ec0a91dd4256c9e54934b3c7095a7ee3
+Merge: b65bd4031156 037f03155b7d

 Author: Dave Airlie <airlied@redhat.com>
 Author: Dave Airlie <airlied@redhat.com>

-Date:   Mon Dec 4 09:40:35 2017 +1000
+Date:   Wed Mar 21 14:07:03 2018 +1000

 
 

-    Merge tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
+    Merge tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next

diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 5597a87154e586ec71151b006af60ad9ffbf2c61..50bcf4214ff9745c3d1aaec55fbef99ea6c5f516 100644 (file)
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -38,14 +38,18 @@ extern "C" {
 #define DRM_DISPLAY_MODE_LEN   32
 #define DRM_PROP_NAME_LEN      32
 
 #define DRM_DISPLAY_MODE_LEN   32
 #define DRM_PROP_NAME_LEN      32
 

-#define DRM_MODE_TYPE_BUILTIN  (1<<0)
-#define DRM_MODE_TYPE_CLOCK_C  ((1<<1) | DRM_MODE_TYPE_BUILTIN)
-#define DRM_MODE_TYPE_CRTC_C   ((1<<2) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_BUILTIN  (1<<0) /* deprecated */
+#define DRM_MODE_TYPE_CLOCK_C  ((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */
+#define DRM_MODE_TYPE_CRTC_C   ((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */

 #define DRM_MODE_TYPE_PREFERRED        (1<<3)
 #define DRM_MODE_TYPE_PREFERRED        (1<<3)

-#define DRM_MODE_TYPE_DEFAULT  (1<<4)
+#define DRM_MODE_TYPE_DEFAULT  (1<<4) /* deprecated */

 #define DRM_MODE_TYPE_USERDEF  (1<<5)
 #define DRM_MODE_TYPE_DRIVER   (1<<6)
 
 #define DRM_MODE_TYPE_USERDEF  (1<<5)
 #define DRM_MODE_TYPE_DRIVER   (1<<6)
 

+#define DRM_MODE_TYPE_ALL      (DRM_MODE_TYPE_PREFERRED |      \
+                                DRM_MODE_TYPE_USERDEF |        \
+                                DRM_MODE_TYPE_DRIVER)
+

 /* Video mode flags */
 /* bit compatible with the xrandr RR_ definitions (bits 0-13)
  *
 /* Video mode flags */
 /* bit compatible with the xrandr RR_ definitions (bits 0-13)
  *


@@ -66,8 +70,8 @@ extern "C" {
 #define DRM_MODE_FLAG_PCSYNC                   (1<<7)
 #define DRM_MODE_FLAG_NCSYNC                   (1<<8)
 #define DRM_MODE_FLAG_HSKEW                    (1<<9) /* hskew provided */
 #define DRM_MODE_FLAG_PCSYNC                   (1<<7)
 #define DRM_MODE_FLAG_NCSYNC                   (1<<8)
 #define DRM_MODE_FLAG_HSKEW                    (1<<9) /* hskew provided */

-#define DRM_MODE_FLAG_BCAST                    (1<<10)
-#define DRM_MODE_FLAG_PIXMUX                   (1<<11)
+#define DRM_MODE_FLAG_BCAST                    (1<<10) /* deprecated */
+#define DRM_MODE_FLAG_PIXMUX                   (1<<11) /* deprecated */

 #define DRM_MODE_FLAG_DBLCLK                   (1<<12)
 #define DRM_MODE_FLAG_CLKDIV2                  (1<<13)
  /*
 #define DRM_MODE_FLAG_DBLCLK                   (1<<12)
 #define DRM_MODE_FLAG_CLKDIV2                  (1<<13)
  /*


@@ -99,6 +103,20 @@ extern "C" {
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
                        (DRM_MODE_PICTURE_ASPECT_16_9<<19)
 
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
                        (DRM_MODE_PICTURE_ASPECT_16_9<<19)
 

+#define  DRM_MODE_FLAG_ALL     (DRM_MODE_FLAG_PHSYNC |         \
+                                DRM_MODE_FLAG_NHSYNC |         \
+                                DRM_MODE_FLAG_PVSYNC |         \
+                                DRM_MODE_FLAG_NVSYNC |         \
+                                DRM_MODE_FLAG_INTERLACE |      \
+                                DRM_MODE_FLAG_DBLSCAN |        \
+                                DRM_MODE_FLAG_CSYNC |          \
+                                DRM_MODE_FLAG_PCSYNC |         \
+                                DRM_MODE_FLAG_NCSYNC |         \
+                                DRM_MODE_FLAG_HSKEW |          \
+                                DRM_MODE_FLAG_DBLCLK |         \
+                                DRM_MODE_FLAG_CLKDIV2 |        \
+                                DRM_MODE_FLAG_3D_MASK)
+

 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
 #define DRM_MODE_DPMS_ON       0
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
 #define DRM_MODE_DPMS_ON       0


@@ -173,6 +191,10 @@ extern "C" {
                DRM_MODE_REFLECT_X | \
                DRM_MODE_REFLECT_Y)
 
                DRM_MODE_REFLECT_X | \
                DRM_MODE_REFLECT_Y)
 

+/* Content Protection Flags */
+#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED  0
+#define DRM_MODE_CONTENT_PROTECTION_DESIRED     1
+#define DRM_MODE_CONTENT_PROTECTION_ENABLED     2

 
 struct drm_mode_modeinfo {
        __u32 clock;
 
 struct drm_mode_modeinfo {
        __u32 clock;


@@ -341,7 +363,7 @@ struct drm_mode_get_connector {
        __u32 pad;
 };
 
        __u32 pad;
 };
 

-#define DRM_MODE_PROP_PENDING  (1<<0)
+#define DRM_MODE_PROP_PENDING  (1<<0) /* deprecated, do not use */

 #define DRM_MODE_PROP_RANGE    (1<<1)
 #define DRM_MODE_PROP_IMMUTABLE        (1<<2)
 #define DRM_MODE_PROP_ENUM     (1<<3) /* enumerated type with text strings */
 #define DRM_MODE_PROP_RANGE    (1<<1)
 #define DRM_MODE_PROP_IMMUTABLE        (1<<2)
 #define DRM_MODE_PROP_ENUM     (1<<3) /* enumerated type with text strings */


@@ -576,8 +598,11 @@ struct drm_mode_crtc_lut {
 };
 
 struct drm_color_ctm {
 };
 
 struct drm_color_ctm {

-       /* Conversion matrix in S31.32 format. */
-       __s64 matrix[9];
+       /*
+        * Conversion matrix in S31.32 sign-magnitude
+        * (not two's complement!) format.
+        */
+       __u64 matrix[9];

 };
 
 struct drm_color_lut {
 };
 
 struct drm_color_lut {

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 7f28eea4035cd736a9fda4583d929d0926cea9b6..16e452aa12d47f6594b718859b8f46cf8d571260 100644 (file)
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -102,6 +102,46 @@ enum drm_i915_gem_engine_class {
        I915_ENGINE_CLASS_INVALID       = -1
 };
 
        I915_ENGINE_CLASS_INVALID       = -1
 };
 

+/**
+ * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
+ *
+ */
+
+enum drm_i915_pmu_engine_sample {
+       I915_SAMPLE_BUSY = 0,
+       I915_SAMPLE_WAIT = 1,
+       I915_SAMPLE_SEMA = 2
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+       (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
+
+#define __I915_PMU_ENGINE(class, instance, sample) \
+       ((class) << I915_PMU_CLASS_SHIFT | \
+       (instance) << I915_PMU_SAMPLE_BITS | \
+       (sample))
+
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+       __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
+
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+       __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
+
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+       __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+
+#define I915_PMU_ACTUAL_FREQUENCY      __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY   __I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS            __I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY         __I915_PMU_OTHER(3)
+
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+

 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255        /* table size 2k - maximum due to use
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255        /* table size 2k - maximum due to use


@@ -278,6 +318,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_OPEN             0x36
 #define DRM_I915_PERF_ADD_CONFIG       0x37
 #define DRM_I915_PERF_REMOVE_CONFIG    0x38
 #define DRM_I915_PERF_OPEN             0x36
 #define DRM_I915_PERF_ADD_CONFIG       0x37
 #define DRM_I915_PERF_REMOVE_CONFIG    0x38

+#define DRM_I915_QUERY                 0x39

 
 #define DRM_IOCTL_I915_INIT            DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH           DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 
 #define DRM_IOCTL_I915_INIT            DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH           DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)


@@ -335,6 +376,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_OPEN       DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG      DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_PERF_OPEN       DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG      DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)

+#define DRM_IOCTL_I915_QUERY                   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.


@@ -1318,7 +1360,9 @@ struct drm_intel_overlay_attrs {
  * active on a given plane.
  */
 
  * active on a given plane.
  */
 

-#define I915_SET_COLORKEY_NONE         (1<<0) /* disable color key matching */
+#define I915_SET_COLORKEY_NONE         (1<<0) /* Deprecated. Instead set
+                                               * flags==0 to disable colorkeying.
+                                               */

 #define I915_SET_COLORKEY_DESTINATION  (1<<1)
 #define I915_SET_COLORKEY_SOURCE       (1<<2)
 struct drm_intel_sprite_colorkey {
 #define I915_SET_COLORKEY_DESTINATION  (1<<1)
 #define I915_SET_COLORKEY_SOURCE       (1<<2)
 struct drm_intel_sprite_colorkey {


@@ -1564,15 +1608,115 @@ struct drm_i915_perf_oa_config {
        __u32 n_flex_regs;
 
        /*
        __u32 n_flex_regs;
 
        /*

-        * These fields are pointers to tuples of u32 values (register
-        * address, value). For example the expected length of the buffer
-        * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+        * These fields are pointers to tuples of u32 values (register address,
+        * value). For example the expected length of the buffer pointed by
+        * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).

         */
        __u64 mux_regs_ptr;
        __u64 boolean_regs_ptr;
        __u64 flex_regs_ptr;
 };
 
         */
        __u64 mux_regs_ptr;
        __u64 boolean_regs_ptr;
        __u64 flex_regs_ptr;
 };
 

+struct drm_i915_query_item {
+       __u64 query_id;
+#define DRM_I915_QUERY_TOPOLOGY_INFO    1
+
+       /*
+        * When set to zero by userspace, this is filled with the size of the
+        * data to be written at the data_ptr pointer. The kernel sets this
+        * value to a negative value to signal an error on a particular query
+        * item.
+        */
+       __s32 length;
+
+       /*
+        * Unused for now. Must be cleared to zero.
+        */
+       __u32 flags;
+
+       /*
+        * Data will be written at the location pointed by data_ptr when the
+        * value of length matches the length of the data to be written by the
+        * kernel.
+        */
+       __u64 data_ptr;
+};
+
+struct drm_i915_query {
+       __u32 num_items;
+
+       /*
+        * Unused for now. Must be cleared to zero.
+        */
+       __u32 flags;
+
+       /*
+        * This points to an array of num_items drm_i915_query_item structures.
+        */
+       __u64 items_ptr;
+};
+
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ *
+ * data: contains the 3 pieces of information :
+ *
+ * - the slice mask with one bit per slice telling whether a slice is
+ *   available. The availability of slice X can be queried with the following
+ *   formula :
+ *
+ *           (data[X / 8] >> (X % 8)) & 1
+ *
+ * - the subslice mask for each slice with one bit per subslice telling
+ *   whether a subslice is available. The availability of subslice Y in slice
+ *   X can be queried with the following formula :
+ *
+ *           (data[subslice_offset +
+ *                 X * subslice_stride +
+ *                 Y / 8] >> (Y % 8)) & 1
+ *
+ * - the EU mask for each subslice in each slice with one bit per EU telling
+ *   whether an EU is available. The availability of EU Z in subslice Y in
+ *   slice X can be queried with the following formula :
+ *
+ *           (data[eu_offset +
+ *                 (X * max_subslices + Y) * eu_stride +
+ *                 Z / 8] >> (Z % 8)) & 1
+ */
+struct drm_i915_query_topology_info {
+       /*
+        * Unused for now. Must be cleared to zero.
+        */
+       __u16 flags;
+
+       __u16 max_slices;
+       __u16 max_subslices;
+       __u16 max_eus_per_subslice;
+
+       /*
+        * Offset in data[] at which the subslice masks are stored.
+        */
+       __u16 subslice_offset;
+
+       /*
+        * Stride at which each of the subslice masks for each slice are
+        * stored.
+        */
+       __u16 subslice_stride;
+
+       /*
+        * Offset in data[] at which the EU masks are stored.
+        */
+       __u16 eu_offset;
+
+       /*
+        * Stride at which each of the EU masks for each subslice are stored.
+        */
+       __u16 eu_stride;
+
+       __u8 data[];
+};
+

 #if defined(__cplusplus)
 }
 #endif
 #if defined(__cplusplus)
 }
 #endif

diff --git a/include/drm-uapi/tegra_drm.h b/include/drm-uapi/tegra_drm.h
index 910cbe02d87344eb4d22993edfe1627d1f03087b..12f9bf848db1375d253a53a0a3580d63c7b4b5f3 100644 (file)
--- a/include/drm-uapi/tegra_drm.h
+++ b/include/drm-uapi/tegra_drm.h
@@ -117,20 +117,6 @@ struct drm_tegra_waitchk {
        __u32 thresh;
 };
 
        __u32 thresh;
 };
 

-#define DRM_TEGRA_FENCE_WAIT   (1 << 0)
-#define DRM_TEGRA_FENCE_EMIT   (1 << 1)
-#define DRM_TEGRA_FENCE_FD     (1 << 2)
-#define DRM_TEGRA_FENCE_FLAGS  (DRM_TEGRA_FENCE_WAIT | \
-                                DRM_TEGRA_FENCE_EMIT | \
-                                DRM_TEGRA_FENCE_FD)
-
-struct drm_tegra_fence {
-       __u32 handle;
-       __u32 flags;
-};
-
-#define DRM_TEGRA_SUBMIT_FLAGS 0
-

 struct drm_tegra_submit {
        __u64 context;
        __u32 num_syncpts;
 struct drm_tegra_submit {
        __u64 context;
        __u32 num_syncpts;


@@ -143,11 +129,9 @@ struct drm_tegra_submit {
        __u64 cmdbufs;
        __u64 relocs;
        __u64 waitchks;
        __u64 cmdbufs;
        __u64 relocs;
        __u64 waitchks;

-       __u32 flags;
-       __u32 num_fences;
-       __u64 fences;
+       __u32 fence;            /* Return value */

 
 

-       __u32 reserved[2];      /* future expansion */
+       __u32 reserved[5];      /* future expansion */

 };
 
 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
 };
 
 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0


@@ -222,4 +206,4 @@ struct drm_tegra_gem_get_flags {
 }
 #endif
 
 }
 #endif
 

-#endif /* _TEGRA_DRM_H_ */
+#endif