Annoyingly, SPIR-V lets you specify all of these fields in either the
TCS or TES, which means that we need to be able to store all of them
for either shader stage. Putting them in a union won't work.
Combining both is an easy solution, and given that the TCS struct only
had a single field, it's pretty inexpensive.
This patch renames the combined struct to "tess" to indicate that it's
for tessellation in general, not one of the two stages.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
unsigned shared_size;
} cs;
unsigned shared_size;
} cs;
+ /* Applies to both TCS and TES. */
struct {
/** The number of vertices in the TCS output patch. */
struct {
/** The number of vertices in the TCS output patch. */
- unsigned vertices_out;
- } tcs;
+ unsigned tcs_vertices_out;
uint32_t primitive_mode; /* GL_TRIANGLES, GL_QUADS or GL_ISOLINES */
enum gl_tess_spacing spacing;
/** Is the vertex order counterclockwise? */
bool ccw;
bool point_mode;
uint32_t primitive_mode; /* GL_TRIANGLES, GL_QUADS or GL_ISOLINES */
enum gl_tess_spacing spacing;
/** Is the vertex order counterclockwise? */
bool ccw;
bool point_mode;
}
/* Fix the disptach mask */
}
/* Fix the disptach mask */
- if (nir->info->tcs.vertices_out % 8) {
+ if (nir->info->tess.tcs_vertices_out % 8) {
bld.CMP(bld.null_reg_ud(), invocation_id,
bld.CMP(bld.null_reg_ud(), invocation_id,
- brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L);
+ brw_imm_ud(nir->info->tess.tcs_vertices_out), BRW_CONDITIONAL_L);
bld.IF(BRW_PREDICATE_NORMAL);
}
emit_nir_code();
bld.IF(BRW_PREDICATE_NORMAL);
}
emit_nir_code();
- if (nir->info->tcs.vertices_out % 8) {
+ if (nir->info->tess.tcs_vertices_out % 8) {
bld.emit(BRW_OPCODE_ENDIF);
}
bld.emit(BRW_OPCODE_ENDIF);
}
nir_builder_init(&b, function->impl);
nir_foreach_block(block, function->impl) {
remap_patch_urb_offsets(block, &b, vue_map,
nir_builder_init(&b, function->impl);
nir_foreach_block(block, function->impl) {
remap_patch_urb_offsets(block, &b, vue_map,
- nir->info->tes.primitive_mode);
+ nir->info->tess.primitive_mode);
TESS_SPACING_FRACTIONAL_EVEN - 1);
prog_data->partitioning =
TESS_SPACING_FRACTIONAL_EVEN - 1);
prog_data->partitioning =
- (enum brw_tess_partitioning) (nir->info->tes.spacing - 1);
+ (enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
- switch (nir->info->tes.primitive_mode) {
+ switch (nir->info->tess.primitive_mode) {
case GL_QUADS:
prog_data->domain = BRW_TESS_DOMAIN_QUAD;
break;
case GL_QUADS:
prog_data->domain = BRW_TESS_DOMAIN_QUAD;
break;
unreachable("invalid domain shader primitive mode");
}
unreachable("invalid domain shader primitive mode");
}
- if (nir->info->tes.point_mode) {
+ if (nir->info->tess.point_mode) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
- } else if (nir->info->tes.primitive_mode == GL_ISOLINES) {
+ } else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
} else {
/* Hardware winding order is backwards from OpenGL */
prog_data->output_topology =
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
} else {
/* Hardware winding order is backwards from OpenGL */
prog_data->output_topology =
- nir->info->tes.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
- : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
+ nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
+ : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
}
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
}
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
nir->info->inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
nir->info->outputs_written = key->outputs_written;
nir->info->inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
nir->info->outputs_written = key->outputs_written;
- nir->info->tcs.vertices_out = key->input_vertices;
+ nir->info->tess.tcs_vertices_out = key->input_vertices;
nir->info->name = ralloc_strdup(nir, "passthrough");
nir->num_uniforms = 8 * sizeof(uint32_t);
nir->info->name = ralloc_strdup(nir, "passthrough");
nir->num_uniforms = 8 * sizeof(uint32_t);
/* We need to specialize our code generation for tessellation levels
* based on the domain the DS is expecting to tessellate.
*/
/* We need to specialize our code generation for tessellation levels
* based on the domain the DS is expecting to tessellate.
*/
- key->tes_primitive_mode = tep->program.info.tes.primitive_mode;
+ key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
key->quads_workaround = brw->gen < 9 &&
key->quads_workaround = brw->gen < 9 &&
- tep->program.info.tes.primitive_mode == GL_QUADS &&
- tep->program.info.tes.spacing == TESS_SPACING_EQUAL;
+ tep->program.info.tess.primitive_mode == GL_QUADS &&
+ tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
if (tcp) {
key->program_string_id = tcp->id;
if (tcp) {
key->program_string_id = tcp->id;
* HS instance dispatched will only have its bottom half doing real
* work, and so we need to disable the upper half:
*/
* HS instance dispatched will only have its bottom half doing real
* work, and so we need to disable the upper half:
*/
- if (nir->info->tcs.vertices_out % 2) {
+ if (nir->info->tess.tcs_vertices_out % 2) {
emit(CMP(dst_null_d(), invocation_id,
emit(CMP(dst_null_d(), invocation_id,
- brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L));
+ brw_imm_ud(nir->info->tess.tcs_vertices_out),
+ BRW_CONDITIONAL_L));
/* Matching ENDIF is in emit_thread_end() */
emit(IF(BRW_PREDICATE_NORMAL));
/* Matching ENDIF is in emit_thread_end() */
emit(IF(BRW_PREDICATE_NORMAL));
vec4_instruction *inst;
current_annotation = "thread end";
vec4_instruction *inst;
current_annotation = "thread end";
- if (nir->info->tcs.vertices_out % 2) {
+ if (nir->info->tess.tcs_vertices_out % 2) {
emit(BRW_OPCODE_ENDIF);
}
emit(BRW_OPCODE_ENDIF);
}
nir = brw_postprocess_nir(nir, compiler, is_scalar);
if (is_scalar)
nir = brw_postprocess_nir(nir, compiler, is_scalar);
if (is_scalar)
- prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 8);
+ prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 8);
- prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 2);
+ prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 2);
/* Compute URB entry size. The maximum allowed URB entry size is 32k.
* That divides up as follows:
/* Compute URB entry size. The maximum allowed URB entry size is 32k.
* That divides up as follows:
unsigned output_size_bytes = 0;
/* Note that the patch header is counted in num_per_patch_slots. */
output_size_bytes += num_per_patch_slots * 16;
unsigned output_size_bytes = 0;
/* Note that the patch header is counted in num_per_patch_slots. */
output_size_bytes += num_per_patch_slots * 16;
- output_size_bytes += nir->info->tcs.vertices_out * num_per_vertex_slots * 16;
+ output_size_bytes += nir->info->tess.tcs_vertices_out *
+ num_per_vertex_slots * 16;
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
dst->CullDistanceArraySize = src->Vert.CullDistanceArraySize;
break;
case MESA_SHADER_TESS_CTRL: {
dst->CullDistanceArraySize = src->Vert.CullDistanceArraySize;
break;
case MESA_SHADER_TESS_CTRL: {
- dst->info.tcs.vertices_out = dst_sh->info.TessCtrl.VerticesOut;
+ dst->info.tess.tcs_vertices_out = dst_sh->info.TessCtrl.VerticesOut;
break;
}
case MESA_SHADER_TESS_EVAL: {
break;
}
case MESA_SHADER_TESS_EVAL: {
- dst->info.tes.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
- dst->info.tes.spacing = dst_sh->info.TessEval.Spacing;
- dst->info.tes.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
- dst->info.tes.point_mode = dst_sh->info.TessEval.PointMode;
+ dst->info.tess.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
+ dst->info.tess.spacing = dst_sh->info.TessEval.Spacing;
+ dst->info.tess.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
+ dst->info.tess.point_mode = dst_sh->info.TessEval.PointMode;
dst->ClipDistanceArraySize = src->TessEval.ClipDistanceArraySize;
dst->CullDistanceArraySize = src->TessEval.CullDistanceArraySize;
break;
dst->ClipDistanceArraySize = src->TessEval.ClipDistanceArraySize;
dst->CullDistanceArraySize = src->TessEval.CullDistanceArraySize;
break;
case STATE_TES_PATCH_VERTICES_IN:
if (ctx->TessCtrlProgram._Current)
case STATE_TES_PATCH_VERTICES_IN:
if (ctx->TessCtrlProgram._Current)
- val[0].i = ctx->TessCtrlProgram._Current->info.tcs.vertices_out;
+ val[0].i = ctx->TessCtrlProgram._Current->info.tess.tcs_vertices_out;
else
val[0].i = ctx->TessCtrlProgram.patch_vertices;
return;
else
val[0].i = ctx->TessCtrlProgram.patch_vertices;
return;
return false;
ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT,
return false;
ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT,
- sttcp->Base.info.tcs.vertices_out);
+ sttcp->Base.info.tess.tcs_vertices_out);
st_translate_program_common(st, &sttcp->Base, sttcp->glsl_to_tgsi, ureg,
PIPE_SHADER_TESS_CTRL, &sttcp->tgsi);
st_translate_program_common(st, &sttcp->Base, sttcp->glsl_to_tgsi, ureg,
PIPE_SHADER_TESS_CTRL, &sttcp->tgsi);
if (ureg == NULL)
return false;
if (ureg == NULL)
return false;
- if (sttep->Base.info.tes.primitive_mode == GL_ISOLINES)
+ if (sttep->Base.info.tess.primitive_mode == GL_ISOLINES)
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE, GL_LINES);
else
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE,
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE, GL_LINES);
else
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE,
- sttep->Base.info.tes.primitive_mode);
+ sttep->Base.info.tess.primitive_mode);
STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
PIPE_TESS_SPACING_FRACTIONAL_EVEN);
ureg_property(ureg, TGSI_PROPERTY_TES_SPACING,
PIPE_TESS_SPACING_FRACTIONAL_EVEN);
ureg_property(ureg, TGSI_PROPERTY_TES_SPACING,
- (sttep->Base.info.tes.spacing + 1) % 3);
+ (sttep->Base.info.tess.spacing + 1) % 3);
ureg_property(ureg, TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
ureg_property(ureg, TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
- !sttep->Base.info.tes.ccw);
+ !sttep->Base.info.tess.ccw);
ureg_property(ureg, TGSI_PROPERTY_TES_POINT_MODE,
ureg_property(ureg, TGSI_PROPERTY_TES_POINT_MODE,
- sttep->Base.info.tes.point_mode);
+ sttep->Base.info.tess.point_mode);
st_translate_program_common(st, &sttep->Base, sttep->glsl_to_tgsi,
ureg, PIPE_SHADER_TESS_EVAL, &sttep->tgsi);
st_translate_program_common(st, &sttep->Base, sttep->glsl_to_tgsi,
ureg, PIPE_SHADER_TESS_EVAL, &sttep->tgsi);