-
-# subtype row_t is integer range 0 to BRAM_ROWS-1;
-# subtype index_t is integer range 0 to NUM_LINES-1;
-"""wherever way_t is used to make a Signal it must be substituted with
- log2_int(NUM_WAYS) i.e. WAY_BITS. this because whilst the *range*
- of the number is 0..NUM_WAYS it requires log2_int(NUM_WAYS) i.e.
- WAY_BITS of space to store it
-"""
-# subtype way_t is integer range 0 to NUM_WAYS-1;
-# subtype row_in_line_t is unsigned(ROW_LINE_BITS-1 downto 0);
- ROW = BRAM_ROWS # yyyeah not really necessary, delete
- INDEX = NUM_LINES # yyyeah not really necessary, delete
- WAY = NUM_WAYS # yyyeah not really necessary, delete
- ROW_IN_LINE = ROW_LINE_BITS # yyyeah not really necessary, delete
-
-# -- The cache data BRAM organized as described above for each way
-# subtype cache_row_t is
-# std_ulogic_vector(wishbone_data_bits-1 downto 0);
- # The cache data BRAM organized as described above for each way
- CACHE_ROW = WB_DATA_BITS
-
-# -- The cache tags LUTRAM has a row per set.
-# -- Vivado is a pain and will not handle a
-# -- clean (commented) definition of the cache
-# -- tags as a 3d memory. For now, work around
-# -- it by putting all the tags
-# subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
- # The cache tags LUTRAM has a row per set.
- # Vivado is a pain and will not handle a
- # clean (commented) definition of the cache
- # tags as a 3d memory. For now, work around
- # it by putting all the tags
- CACHE_TAG = TAG_BITS
-
-# -- type cache_tags_set_t is array(way_t) of cache_tag_t;
-# -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
-# constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
-# subtype cache_tags_set_t is
-# std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
-# type cache_tags_array_t is array(index_t) of cache_tags_set_t;
- # type cache_tags_set_t is array(way_t) of cache_tag_t;
- # type cache_tags_array_t is array(index_t) of cache_tags_set_t;