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liteeth: pep8 (E222)
author
Florent Kermarrec
<florent@enjoy-digital.fr>
Mon, 13 Apr 2015 08:48:59 +0000
(10:48 +0200)
committer
Florent Kermarrec
<florent@enjoy-digital.fr>
Mon, 13 Apr 2015 08:48:59 +0000
(10:48 +0200)
misoclib/com/liteeth/core/etherbone/record.py
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|
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|
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misoclib/com/liteeth/example_designs/make.py
patch
|
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misoclib/com/liteeth/generic/depacketizer.py
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misoclib/com/liteeth/mac/core/__init__.py
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diff --git
a/misoclib/com/liteeth/core/etherbone/record.py
b/misoclib/com/liteeth/core/etherbone/record.py
index 09f9b1985b2098b34dbe5e35c3d25d1228b97da1..90d98a50e7a86f6597571082cdc5ef3d7f2b4645 100644
(file)
--- a/
misoclib/com/liteeth/core/etherbone/record.py
+++ b/
misoclib/com/liteeth/core/etherbone/record.py
@@
-152,7
+152,7
@@
class LiteEthEtherboneRecord(Module):
# receive record, decode it and generate mmap stream
self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
# receive record, decode it and generate mmap stream
self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
- self.submodules.receiver = receiver =
LiteEthEtherboneRecordReceiver()
+ self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
self.comb += [
Record.connect(sink, depacketizer.sink),
Record.connect(depacketizer.source, receiver.sink)
self.comb += [
Record.connect(sink, depacketizer.sink),
Record.connect(depacketizer.source, receiver.sink)
@@
-169,7
+169,7
@@
class LiteEthEtherboneRecord(Module):
]
# receive mmap stream, encode it and send records
]
# receive mmap stream, encode it and send records
- self.submodules.sender = sender =
LiteEthEtherboneRecordSender()
+ self.submodules.sender = sender = LiteEthEtherboneRecordSender()
self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
self.comb += [
Record.connect(sender.source, packetizer.sink),
self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
self.comb += [
Record.connect(sender.source, packetizer.sink),
diff --git
a/misoclib/com/liteeth/example_designs/make.py
b/misoclib/com/liteeth/example_designs/make.py
index caf6a293bdf1dbd3416faaffe23ef2fc9e55f4e6..a297da5bf838f87b3c3d896149ef24aa8e12bf8b 100644
(file)
--- a/
misoclib/com/liteeth/example_designs/make.py
+++ b/
misoclib/com/liteeth/example_designs/make.py
@@
-75,7
+75,7
@@
if __name__ == "__main__":
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs)
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs)
- build_name = top_class.__name__.lower() +
"-" + platform_name
+ build_name = top_class.__name__.lower() + "-" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
diff --git
a/misoclib/com/liteeth/generic/depacketizer.py
b/misoclib/com/liteeth/generic/depacketizer.py
index c6e13dffa2b3380b2f6a14b2d5bb4e7003399f01..49d1cf80ec17f21be4f218b804724004fc7d3974 100644
(file)
--- a/
misoclib/com/liteeth/generic/depacketizer.py
+++ b/
misoclib/com/liteeth/generic/depacketizer.py
@@
-80,7
+80,7
@@
class LiteEthDepacketizer(Module):
fsm.act("COPY",
sink.ack.eq(source.ack),
source.stb.eq(sink.stb | no_payload),
fsm.act("COPY",
sink.ack.eq(source.ack),
source.stb.eq(sink.stb | no_payload),
- If(source.stb &
source.ack & source.eop,
+ If(source.stb & source.ack & source.eop,
NextState("IDLE")
)
)
NextState("IDLE")
)
)
diff --git
a/misoclib/com/liteeth/mac/core/__init__.py
b/misoclib/com/liteeth/mac/core/__init__.py
index da512aeec526f97a5209da143e527a09780f4c89..127d645d8ce5acc7eedac5d304d7c44475ff7d95 100644
(file)
--- a/
misoclib/com/liteeth/mac/core/__init__.py
+++ b/
misoclib/com/liteeth/mac/core/__init__.py
@@
-79,8
+79,8
@@
class LiteEthMACCore(Module, AutoCSR):
# Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
# Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
- self.submodules +=
RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
- self.submodules +=
RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
+ self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
+ self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
tx_pipeline += [tx_cdc]
rx_pipeline += [rx_cdc]
tx_pipeline += [tx_cdc]
rx_pipeline += [rx_cdc]