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include *all* fprs/gprs/cr-fields in SimState
author
Jacob Lifshay
<programmerjake@gmail.com>
Wed, 14 Sep 2022 15:33:55 +0000
(08:33 -0700)
committer
Jacob Lifshay
<programmerjake@gmail.com>
Wed, 14 Sep 2022 15:33:55 +0000
(08:33 -0700)
src/openpower/test/state.py
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diff --git
a/src/openpower/test/state.py
b/src/openpower/test/state.py
index 7bc796892f3a2f9dc11eba5db6550750d1497165..07827e76a66423caa739db53c1df9fc35d6cd3b2 100644
(file)
--- a/
src/openpower/test/state.py
+++ b/
src/openpower/test/state.py
@@
-186,6
+186,16
@@
class State:
sout.close()
sout.close()
+def _get_regs(regs, asint=lambda v: v.asint()):
+ retval = []
+ while True:
+ try:
+ retval.append(asint(regs[len(retval)]))
+ except (IndexError, KeyError):
+ break
+ return retval
+
+
class SimState(State):
"""SimState: Obtains registers and memory from an ISACaller object.
Note that yields are "faked" to maintain consistency and compatibility
class SimState(State):
"""SimState: Obtains registers and memory from an ISACaller object.
Note that yields are "faked" to maintain consistency and compatibility
@@
-197,28
+207,19
@@
class SimState(State):
def get_fpregs(self):
if False:
yield
def get_fpregs(self):
if False:
yield
- self.fpregs = []
- for i in range(32):
- simregval = self.sim.fpr[i].asint()
- self.fpregs.append(simregval)
+ self.fpregs = _get_regs(self.sim.fpr)
log("class sim fp regs", list(map(hex, self.fpregs)))
def get_intregs(self):
if False:
yield
log("class sim fp regs", list(map(hex, self.fpregs)))
def get_intregs(self):
if False:
yield
- self.intregs = []
- for i in range(32):
- simregval = self.sim.gpr[i].asint()
- self.intregs.append(simregval)
+ self.intregs = _get_regs(self.sim.gpr)
log("class sim int regs", list(map(hex, self.intregs)))
def get_crregs(self):
if False:
yield
log("class sim int regs", list(map(hex, self.intregs)))
def get_crregs(self):
if False:
yield
- self.crregs = []
- for i in range(8):
- cri = self.sim.crl[i].get_range().value
- self.crregs.append(cri)
+ self.crregs = _get_regs(self.sim.crl, lambda v: v.get_range().value)
log("class sim cr regs", list(map(hex, self.crregs)))
def get_xregs(self):
log("class sim cr regs", list(map(hex, self.crregs)))
def get_xregs(self):