(no commit message)

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index 31c187a0a4fe76a6a611968e0fc142f159b90f33..27417ece899f278fc312d381a2bc65cc942144e7 100644 (file)
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -19,7 +19,7 @@ To be expanded with links to bugreports
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache

-* interfaces we need as a bare minimum include GPIO, EINT, SPI and QSPI,
+* [[180nm_oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,

   I2C, UART16550, LPC (from Raptor Engineering) and that actually might
   even be it.
 
   I2C, UART16550, LPC (from Raptor Engineering) and that actually might
   even be it.