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author
lkcl
<lkcl@web>
Sat, 23 Oct 2021 21:05:30 +0000
(22:05 +0100)
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IkiWiki
<ikiwiki.info>
Sat, 23 Oct 2021 21:05:30 +0000
(22:05 +0100)
3d_gpu/architecture/dynamic_simd/slice.mdwn
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diff --git
a/3d_gpu/architecture/dynamic_simd/slice.mdwn
b/3d_gpu/architecture/dynamic_simd/slice.mdwn
index 1947b283ab4587737b06f774e7fbdc6f9de7d08b..54128e02d8f954d476dcb4e88c49d5d186a6dfdf 100644
(file)
--- a/
3d_gpu/architecture/dynamic_simd/slice.mdwn
+++ b/
3d_gpu/architecture/dynamic_simd/slice.mdwn
@@
-215,6
+215,15
@@
PartitionedAdd may be deployed because both the overall
width and the positions of the PartitionPoints are exactly
matched.
width and the positions of the PartitionPoints are exactly
matched.
+Another example: Cat() on the same 2 signals: here at least we
+know that the end-result is elements of 5 bits each, because
+all "a" slices are 3 bit and all "b" elements are 2 bit:
+
+ elwid | | | | | | |
+ 0b00 x x x x x x x x x x x x x x x x x x x x x A2A1A0
+ 0b01 x x x x x x x B5B4AaA9A8 x x x x x x x x x A2A1A0
+ 0b10 x B7B6AeAdAc x B5B4AaA9A8 x B3B2A6A5A4 x B1B0A2A1A0
+
Illustrating the case where a Sliced (fixed element width) SimdSignal
is added to one which has variable-length elements that take up the
Illustrating the case where a Sliced (fixed element width) SimdSignal
is added to one which has variable-length elements that take up the