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add extra info
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 5 Aug 2018 12:36:26 +0000
(13:36 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 5 Aug 2018 12:36:26 +0000
(13:36 +0100)
interrupts.mdwn
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diff --git
a/interrupts.mdwn
b/interrupts.mdwn
index f62af414839fb464f6e8f50b8ef94502e6a94d3c..300ed7b1897480333be4dc1426c71e474cb1b6ca 100644
(file)
--- a/
interrupts.mdwn
+++ b/
interrupts.mdwn
@@
-9,6
+9,10
@@
of interrupt handling is here: [[interrupt_handling]].
* <https://github.com/RoaLogic/plic> - written in verilog, has an
AHB3-Lite / AMBA interface. Documentation is here:
<https://github.com/RoaLogic/plic/blob/master/DATASHEET.md>
* <https://github.com/RoaLogic/plic> - written in verilog, has an
AHB3-Lite / AMBA interface. Documentation is here:
<https://github.com/RoaLogic/plic/blob/master/DATASHEET.md>
+ It has been taped out, it supports virtually unlimited (limited by
+ timing only) IRQ lines. All registers are dynamically generated.
+ Currently it only features an AHB3 slave interface, but the BIU is
+ separate. So other interfaces can be easily added.
* Shakti Peripherals, there is a tested (taped-out) version here
in src/peripherals/plic <https://bitbucket.org/casl/c-class/src/>
and another version with up to 1024 IRQ lines and a 2-cycle
* Shakti Peripherals, there is a tested (taped-out) version here
in src/peripherals/plic <https://bitbucket.org/casl/c-class/src/>
and another version with up to 1024 IRQ lines and a 2-cycle