+void
+ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p,
+ struct intel_bo *bo, int index)
+{
+ uint32_t regs[] = {
+ IA_VERTICES_COUNT,
+ IA_PRIMITIVES_COUNT,
+ VS_INVOCATION_COUNT,
+ GS_INVOCATION_COUNT,
+ GS_PRIMITIVES_COUNT,
+ CL_INVOCATION_COUNT,
+ CL_PRIMITIVES_COUNT,
+ PS_INVOCATION_COUNT,
+ p->dev->gen >= ILO_GEN(7) ? HS_INVOCATION_COUNT : 0,
+ p->dev->gen >= ILO_GEN(7) ? DS_INVOCATION_COUNT : 0,
+ 0,
+ };
+ int i;
+
+ p->emit_flush(p);
+
+ for (i = 0; i < Elements(regs); i++) {
+ const uint32_t bo_offset = (index + i) * sizeof(uint64_t);
+
+ if (regs[i]) {
+ /* store lower 32 bits */
+ gen6_emit_MI_STORE_REGISTER_MEM(p->dev,
+ bo, bo_offset, regs[i], p->cp);
+ /* store higher 32 bits */
+ gen6_emit_MI_STORE_REGISTER_MEM(p->dev,
+ bo, bo_offset + 4, regs[i] + 4, p->cp);
+ }
+ else {
+ gen6_emit_MI_STORE_DATA_IMM(p->dev,
+ bo, bo_offset, 0, true, p->cp);
+ }
+ }
+}
+