-(define_expand "clz<mode>2"
- [(set (match_operand:SIDI 0 "register_operand" "")
- (clz:SIDI (match_operand:SIDI 1 "register_operand" "")))]
+(define_expand "popcountsi2"
+ [(set (match_dup 2)
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
+ (set (match_operand:SI 0 "register_operand" "")
+ (truncate:SI (popcount:DI (match_dup 2))))]
+ "TARGET_POPC"
+{
+ if (! TARGET_ARCH64)
+ {
+ emit_insn (gen_popcountsi_v8plus (operands[0], operands[1]));
+ DONE;
+ }
+ else
+ operands[2] = gen_reg_rtx (DImode);
+})
+
+(define_insn "*popcountsi_sp64"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (truncate:SI
+ (popcount:DI (match_operand:DI 1 "register_operand" "r"))))]
+ "TARGET_POPC && TARGET_ARCH64"
+ "popc\t%1, %0")
+
+(define_insn "popcountsi_v8plus"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (popcount:SI (match_operand:SI 1 "register_operand" "r")))]
+ "TARGET_POPC && ! TARGET_ARCH64"
+{
+ if (sparc_check_64 (operands[1], insn) <= 0)
+ output_asm_insn ("srl\t%1, 0, %1", operands);
+ return "popc\t%1, %0";
+}
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
+
+(define_expand "clzdi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (clz:DI (match_operand:DI 1 "register_operand" "")))]