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Fix gdb protocol register read of S0
author
Brian Campbell
<Brian.Campbell@ed.ac.uk>
Mon, 19 Dec 2016 17:54:19 +0000
(17:54 +0000)
committer
Brian Campbell
<Brian.Campbell@ed.ac.uk>
Wed, 21 Dec 2016 11:37:33 +0000
(11:37 +0000)
riscv/gdbserver.cc
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diff --git
a/riscv/gdbserver.cc
b/riscv/gdbserver.cc
index 3e68872b3cbcb52310921d431f3deced74eccea8..c4e0fefad11b68f54e0e49df68dfe68d43438864 100644
(file)
--- a/
riscv/gdbserver.cc
+++ b/
riscv/gdbserver.cc
@@
-592,12
+592,16
@@
class register_read_op_t : public operation_t
switch (step) {
case 0:
if (reg >= REG_XPR0 && reg <= REG_XPR31) {
switch (step) {
case 0:
if (reg >= REG_XPR0 && reg <= REG_XPR31) {
+ unsigned int i = 0;
+ if (reg == S0) {
+ gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
+ }
if (gs.xlen == 32) {
if (gs.xlen == 32) {
- gs.dr_write32(
0
, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(
i++
, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
} else {
} else {
- gs.dr_write32(
0
, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(
i++
, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
}
}
- gs.dr_write_jump(
1
);
+ gs.dr_write_jump(
i
);
} else if (reg == REG_PC) {
gs.start_packet();
if (gs.xlen == 32) {
} else if (reg == REG_PC) {
gs.start_packet();
if (gs.xlen == 32) {